Monolithic RFIC Design

Part II. RF Circuit Design

Reference books:

1. Thomas H. Lee, The Design of CMOS Radio-Frequency

Integrated Circuits, 2nd ed., Cambridge university press, 2004;

2. B. Razavi, RF Microelectronics, Prentice Hall PTR, 1998.

3. Frank Ellinger, Radio Frequency Integrated Circuits and Technology,

Springer-Verlag, 2006.

T.H.Huang
 Chapter 06

Low-Noise Amplifier Design

1. Introduction : different system applications

2. General Considerations : Noise, Noise match
Impedance (Power) match
3. Performance Evaluation Parameters : Gain,
Linearity,
Noise Figure,
Stability Factor
4. Introduction to LNA Topologies
RF Applications:

1. Cellular :  (1G) : AMPS

 (2G) : GSM, PCS, IS-54/IS-136 (NADC), IS-95(CDMA)
 (2.5G) : GPRS / EDGE (2.5G)
 (3G) : W-CDMA
 (4G): http://zh.wikipedia.org/wiki/4G

2. Non-Cellular : WLAN, Bluetooth, WPAN, UWB, WBN

GPRS : General Packet Radio Service

EDGE : Enhanced Data Rates for GSM Evolution
 Some Characteristics of AMPS: (Analog-type)

Advanced Mobile Phone Service (AMPS)

Parameter Value
Mobile-to-Base Frequency 824-849 MHz
Base-to-Mobile Frequency 869-894 MHz
Channel Spacing 30 kHz
Multiple access method FDMA

FDD: Duplex Method FDD

using different
frequencies for
Users per channel 1
transmitting & Modulation Methodology FM
receiving.
 Some Characteristics of GSM-900: (Digital-type)

Global System for Mobile Communications (GSM-900)

Parameter Value
Mobile-to-Base Frequency 880-915 MHz
Base-to-Mobile Frequency 925-960 MHz
Channel Spacing 200 kHz
Multiple access method TDMA/FDM
Duplex Method FDD
Users per channel 8
B:
filter’s bandwidth. Modulation Methodology GMSK; BT=0.3
T:
bit period (time). Channel bit rate 270.833 kb/s
 Some Characteristics of GSM-1800:

Global System for Mobile Communications (GSM-1800)

Parameter Value
Only freq. ↑ Mobile-to-Base Frequency 1710-1785 MHz
as compared
with GSM-900. Base-to-Mobile Frequency 1805-1880 MHz
Channel Spacing 200 kHz
Multiple access method TDMA/FDM
Duplex Method FDD
Users per channel 8
Modulation Methodology GMSK; BT=0.3
Channel bit rate 270.833 kb/s
Some Characteristics of PCS-1900: (in USA)

Personal Communication System (PCS-1900)

Parameter Value
Mobile-to-base Frequency 1850-1910 MHz
Base-to-Mobile Frequency 1930-1990 MHz
Channel Spacing 200 kHz
Multiple access method TDMA/FDM
Duplex Method FDD
Users per channel 8
Modulation Methodology GMSK; BT=0.3
Channel bit rate 270.833 kb/s
Some Characteristics of IS-54/-136:

North American Digital Cellular (NADC; IS-54/-136)

Parameter Value
Mobile-to-base Frequency 824-849 / 1850-1910 MHz
Base-to-Mobile Frequency 869-894 / 1930-1990 MHz
Channel Spacing / Numbers 30 kHz / 832 / 1999
Multiple access method TDMA/FDM
Duplex Method FDD
Users per channel 3
Modulation Methodology π/4-DQPSK
Channel bit rate 48.6 kb/s
Some Characteristics of IS-95 CDMA: (by Qualcomm. Corp.)

Code Division Multiple Access (CDMA)

Parameter Value
Mobile-to-base Frequency *(see below)
Base-to-Mobile Frequency *(see below)
Channel Spacing / Number 1250 kHz / 20 / 48 / 48
Multiple access method CDMA / FDM
Duplex Method FDD
Users per channel 15 - ?
Modulation Methodology QPSK / OQPSK
Channel bit rate (chip rate) 1.2288 Mb/s
 CDMA Operation Frequencies:

800 MHz 1900 MHz Asia (*)

__________________________________________

Mobile-to-base 824 – 849 1850 – 1910 1920 – 1980

Base-to-mobile 869 – 894 1930 – 1990 2110 – 2170

* For example:
•Japan : DoCoMo
•Korea : Samsung
Requirements of 3G (W-CDMA, CDMA-2000, UMTS):

•high-speed digital communication, not voice-centric;

•144 kb/s in-vehicle data rates (a moving car);
•Up to 384 kb/s for pedestrians (a walker);
•Other issues like what in 2G CDMA.

The next generation – 4G:

•Using W-OFDM modulation methodology;

•Higher data rates then W-CDMA.
•http://zh.wikipedia.org/wiki/4G
Summary of IEEE 802.11b/a/g:

Wireless Local Area Network (WLAN)

Parameter 802.11 b 802.11 g 802.11 a
5150-5350 MHz
Operation Frequency 2400-2483.5MHz 5725-5825 MHz
FHSS: 1MHz
Channel Spacing OFDM: 20 MHz
DSSS: 25MHz
Channel Numbers 3 non-overlapping 12 non-
overlapping
Multiple access method CSMA / CA

Duplex Method TDD

Modulation Methodology FHSS: GFSK, OFDM: 64-QAM for 54 Mb/s

BT=0.5
12 Ms/s
bit rate (or symbol rate) 1,2, 11 Mb/s 54 Mb/s 5.5-54 Mb/s
Summary of Bluetooth:

Bluetooth
Parameter Value
Frequency Range 2402 – 2480 MHz

Channel Spacing / Number 1 MHz / 79

Multiple access method Frequency Hop
Duplex Method TDD
Users per channel 200 (7 active)
Modulation Methodology GFSK
Symbol rate 1 MS/s
Summary of IEEE 802.15.4 (ZigBee):

Wireless Personal Area Network (WPAN) -- ZigBee

Parameter Value
Frequency range (USA) 2402 – 2480 MHz / 902-928 MHz

Frequency range (Europe) 2412-2472 MHz

Channel Spacing 5 MHz
Multiple access method CSMA / CA / CD / TDMA CSMA : Carrier Sense …
CA : Collision Avoidance
Duplex Method FDD CD : Collision Detection

Users per channel 255

Modulation Methodology OQPSK / GFSK / BT=0.5
Peak bit rate 250 / 40 / 250 kb/s
Ultra-Wide Band (UWB): from 3,168 MHz – 10,560 MHz
2 f H  f L 
1. fractional BW   0.25 (or 0.2);
fH  fL 
•Definitions: 2. operation frequency  6 GHz; and tuning range  1.5 G
3. BW  500 MHz as operation frequency  2.5 GHz

DS-CDMA :

MB-OFDM :
Low Noise Amplifier:

•Commonly, the first stage of a receiver for any system

•The requirement of “low noise” and “high gain”
in the first stage:

Noise
Noise Figure of m - Cascaded Stages :

 F2  1  F3  1  Fm  1
 
Ftotal  1  F1  1    m (Friis equation)
G1 G1G2  Gn
n 1

where
Fm is the noise factor in linear (not in dB) of the m - th stage,
G n is the power gain in linear (not in dB), too.
Cascaded Nonlinear Stages:
Consider two nonlinear stages in cascade.
Linearity
Let y1 (t)  α1x(t)  α 2 x 2 (t)  α 3 x 3 (t)  
(to next stage)

y 2 (t)  β1 y1 (t)  β 2 y12 (t)  β 3 y13 (t)  


y 2 (t)  α1 β1 x(t)  (α 3β1  2α1α 2β 2  α13β 3 )x 3 (t)  
4 α1 β1
IIP3  (not in dB, Lecture P.63)
3 (α 3β1  2α1α 2β 2  α13β 3 )
The worst - case, IIP3 is about
3 α 3β1  2α1α 2β 2  α1β 3
3
1 1 3 α 2β 2 α12
   
 IIP3 4
2
α1 β1  IIP31 2 β1  IIP3 22
2
Cascaded Nonlinear Stages: (cont.)

The worst - case, IIP3 for a two cascaded stages is :

1 3 2  2
1 12 1 12
    
 IIP3  IIP31 2 1  IIP3 2  IIP31  IIP3 22
2 2 2 2

Similarly , for a n - cascade stage :

1 1 12 12 12 12 12 
   
 IIP3 2
total  IIP3 12   IIP3 2
2 
IIP3 32   IIP3 2n
1 G12 G12G22 G12G22  Gn21
   
 IIP3 12   IIP3 2
2  2
IIP3 3   IIP3 2n
Note : 1  G1 , 1  G2  are the linear (voltage) gain (not in dB) of
the n - th stage gain.
Brief Summary:
LNA: trade-offs between Gain, Noise, and Linearity

•For “noise” consideration :

The first stage must be “high gain” and “less noise”
to achieve the overall low-noise performance;

•For “linearity” consideration :

The latest stage must be with “high IIP3” to
achieve the overall better linearity performance.
< 應用 Agilent AppCAD 3.0>
General Considerations for LNAs:

-- Gain : impedance (power) match

-- Noise : Noise match
-- Linearity : IIP3 / OIP3
-- Stability : amplifier   oscillator
-- Power consumption (low voltage / low power)

Questions: Why to enlarge the power gain?

Why you need low noise?
Why we need concern about the linearity?
Correlation between the linearity and the power?
Power match:

•Maximum power translation:

Rs Vin Vin2 VS2 1  RL 
2

Pin ( RL )    
+ 2 RL 2 RL  RS  RL 
Vs RL
 VS2 1  RL RL
    PS
-  2 RS  RL  RS  RL RS  RL
 1
Pin ( RL )  0  Pin,max  PS @ R L  R S .
Zs Zin RL 2

•Conjugate match:
Typically, input
Z S  RS  jX S match = 50 Ω for LNA,
Z in  Z S*  RS  jX S because of filter or
antenna.
 Z S  Z in  RS  RS
(maximum power translation)
 Input match for CS amplifier

> Rs : the signal source resistance;

> Let R1 (equivalent bias R)  50 Ω

∞ > Adding R1, Thermal noise ↑

Input signal power (V-swing) @ gate ↓
> In general, “noise figure” degrades.
But recall the noise circle vs. gain

circle behavior  maybe cause a

better noise figure overall.
(impedance dependent noise match)
Typically, the lower bound on the noise of this circuit:
4γ 1
Noise Figure, F  2   where R s  R 1  R
α gmR
Input match for CS amplifier using negative feedback:

1. Broadband “real” input impedance;

2. Better than the amplifier (Fig.11.1)
in noise figure, because of
no signal degrade at gate terminal.
(using self-bias, V-swing can be
greater.)
3. In UWB application*. (conceptive)
 CG amplifier:

1. Input impedance ~ 1/gm

2. Easy to match to 50 Ω
3. Low-power gain issue.

Typically, the lower bound on the noise of this circuit:

γ
Noise Figure, F  1 
α
Summary of Different Types of Amplifiers:

Types of Amplifiers Rin Rout (Voltage) Gain

______________________________________________

CS High High High

CG Low Medium Low

CD Medium Low Low

Feedback Configurations:

Negative Feedback Features:

1. Desensitize the gain : ex. temperature effect.

2. Reduce nonlinear distortion : degeneration, gain constant.
3. Reduce the effect of noise : extra mechanism to compensate noise.
4. Control the input and output impedance : to correlate the I/O resistances.
5. Extend the bandwidth of the amplifier.
Noise reduction using negative feedback: [ 前題 : 需有前級 LNA]

S/N  Vs /Vn

(LNA, better if noiseless) A1A 2 A1

Vo  Vs   Vn
1  β  A1A 2 1  β  A1A 2
S Vs
  A2
N Vn
 •Summary of Four Basic Feedback Configurations:

Input Output
Input Output (Mixing) (Sensing) Rin Rout

Voltage Amp. Vi Vo series shunt

Trans-G Amp. Vi Io series series

Trans-R Amp. Ii Vo shunt shunt

Current Amp. Ii Io shunt series

Increase / decrease factor : 1   A

A reason of “resistive component” arising from the gate capacitance:

Question: Why the input impedance of a MOSFET has a

resistance component from the AC viewpoint?

1
(gate-to-drain cap.) Z in   Miller Effect
sC[1  A( s )]
if A(s) have gain and phase shift, A(s)  A 0 e  j
then
1 1
Z in  
 
j  C 1  A0 e  j  j  C 1  A0 (cos   j sin  )
1
Yin   j  C 1  A0 (cos   j sin  )
Z in
 Re( Yin )  j Im (Yin )
 possesses a real part  behave like a resistor
Input impedance due to the source degeneration:

1
Zin   1  β j ω   Z
j ω Cgs


1
j ω Cgs
 
 1  β 0e  j (ω t  φ) Z
Z

1. Capacitive degeneration
 becomes a negative resistance
2. Inductive degeneration
 becomes a positive resistance.
Inductive degeneration in a CS amplifier:

gm 1
Z in  sL(1  )
sC gs sC
gm 1
 L  ( sL  )
C gs sC gs
 Re (Zin )  j Im(Zin )

• L can be converted into

a real part ( a resistor) and
!! A popular scheme !! adjusted to match 50 Ω.
Brief Summary:

1. Impedance match can be done by source degeneration;

2. This converted resistance brings no thermal noise,
because it is not a real resistor! (very important!)
3. No extra thermal noise is introduced;
4. To utilize this method to do either “power match” or
“noise match”, or even both.
5. However, this is a “narrow band” matching.

[to be continued]
Intrinsic MOSFET Two-Port Noise Parameters: (*ref[1], Ch12.2)

2
ind  4kT  g do f
(drain current noise)
i2
ng  4kT  g g f
(gate current noise)
where
 2C gs2
gg  ( from fitting )
5 g do
there the gate noise is correlated with the drain noise,
with a correlation coefficient as
i ng  i*nd
c   j 0.395 (assumption, for long - channel)
i i
2
ng
2
nd
Four equivalent two-port noise parameters:
1. input referred drain current noise :
i 2
 g do
en  2  4kT 2 f
2 nd

gm gm
2. four noise parameters :
en2  g do
Rn   2
4kT f gm
iu2
Gu   uncorrelated
4kT f
Gc  Re[Yc ]
ic
Bc  Im[Yc ] where Yc   correlated
en
Open-Circuit Drain Current Noise:

1. Assumed that the input admittance of a MOSFET

is purely capacitive.
2
in1 ind2
  en ,open  2
2

(j C gs ) 2
gm
2 ind2 (j C gs ) 2
 in1   en
2
(j  C gs ) 2

g m2
2. The induced gate noise current itself consists of two terms,
i ngc  the fully correlated gate current with the drain current noise.
i ngu  the fully uncorrelated gate current with the drain current noise.
3. The correlated admittance :
i i i g
Yc  n1 ngc  j  C gs  ngc  j  C ge  ingc m
en en ind
 gm ( 推導過程 )
Yc  j  C gs  ingc
ind
ingc  ind
*
ingc  ind
*
ing2
 j  C gs  g m  j  C gs  g m
ind  i *
nd
2
ind ing2

ingc  ind
*
ing2 ingc  ind
*
ing2
 j  C gs  g m 2
 j  C gs  g m
i 2
nd i2
nd
ing ing2 ind2 ind2

ing2   2C gs2
 j  C gs  g m c  j  C gs  g m c
ind2 5  g do
2

gm 
 j  C gs  c  C gs  assumed c is  j c
g do 5
gm  
 j  C gs  j c  C gs  j  C gs (1   c )
g do 5 5
gm
where    1 (for long - channel,   1)
g do
 1. Since Yc (the correlation admittance) is pure imaginary,

so that Gc = 0. (assumption in this modeling case)

2. The induced gate noise :
2 2
i  (ingc  ignu )  4kT g g f c  4kT g g f (1  c )
2
ng
2

(correlated) (uncorrelated)

3. The uncorrelated portion of the gate noise current makes

2 2
2
i 4kT  g g f (1  c )   2C gs2 (1  c )
Gu  u
 
4kT f 4kT f 5 g do

4. To achieve the minimum noise figure Bopt = -Bc = -Im[Yc]

5. Bopt is negative, it means that the optimum source susceptance
is essentially inductive in character.

6. The real part of the optimum source admittance is:

Gu  2 Gu iu2
Gopt   Gc2    C gs (1  c ) , where   Gu2
Rn 5 Rn en2

7. The minimum noise figure is given by:

2  2
Fmin  1  2 Rn [Gopt  Gc ]  1    (1  c )
5 T
*Ways to minimum
gm
where T  . the Fmin by
C gs
* As ωT ↑, Fmin ↓
A General Guide to minimize the device noise:
W W
1. Scaling rule of noise: Gc  Gco Bc  Bco
Wo Wo
W
Gu  Guo
Wo
Wo
Rn  Rno
W

2. That means we can using a unit cell as our circuit design

base, and just only to characterize this noise parameters of
such unit cell.

3. Using the above scaling rule for different sizes of devices.

A General Guide to minimize the device noise: (cont.)

5. Device layout structure  multi-finger, two-side contacts

to reduce the gate “resistance” to reduce the thermal
noise.

•注意 : a. 上述的公式推導乃基於輸入端阻抗為純虛部的假設，
太理想化。
b. 真實元件中，有實部的阻抗產生，會劣化雜訊表現。
Noise Simulation : A macro-model to accommodate the induced gate noise

-- the drain current induced gate noise:

-- most MOS models do not accommodate the induced gate
noise.
M1, M2, M3
are identical!
M2 & M3 are
uncorrelated.

Current-controlled
current source
1. Two replica devices under the same bias condition;
2. Using current-controlled current source (CCCS) to introduce
the noisy drain current into the gate circuits of those
replica devices;
3. Using voltage-controlled voltage sources (VCVS) to ensure
the same bias conditions;
4. Each replica possesses a provision for feeding back
its own noisy drain current to its own gate node.
5. Summation of the two noise (and fully uncorrelated)
currents there results in a noisy voltage at the gate
of M2 (or at M3 with the similar expression):

4kT f 8kT f •Combined

v 2
g2 2  (  v g2 3 ) M1’s and M2’s
g do gm
noises.
for long channel, g do  g m .
6. The noisy gate voltage causes to flow a noisy gate current
of mean-square value:

8kT f
i g2 2   [ (C gs  C gd )]2 ( i g23 )  eq.1 
gm

7. Since
ig 2  (id 2  id 1 ) , thus ig 2 is correlated with id 1.
ig 3  (id 3  id 1 ) , thus ig 3 is also correlated with id 1.

8. Therefore,

ig 2  ig 3 becomes a new noise current

which is uncorrelated with id 1 !
9. After subtraction, the difference current must be scaled
appropriately to produce the correct noise current level
of
4kT f
i g2   [ C gs ]2  eq.2 
5g m

10. Let these two last two equations equal to each other,
we can have the scale factor K:

1
K
C gd
5 (1  )
C gs
where assumed  /   2 for long - channel device.

[to be continued]
Transistor Size Effect:
-- Four noise parameters are scalable  Noise factor (F)
is therefore independent of width. (Note: this is based on
the concept of the use of unit cell.)

-- In general,
Low-power small
medium
trend size
size large
NF (dB)

size

Enhanced
by process

Log(ID)
Power-Constrained As known the four noise parameters :
Noise Optimization: R
F  Fmin  n [(Gs  Gopt ) 2  ( Bs  Bopt ) 2 ]
Gs
Assumed that the source susceptance Bs  Bopt already,
Rn
F  Fmin  [(Gs  Gopt ) 2 ]
Gs
By defining
Gopt  2 1
Q opt   (1  c ) and Q
 C gs 5  C gs Rs

 1 1
F  Fmin  (Qs  C gs  Qopt  C gs ) 2
 g m Qs  C gs
2
    Qopt 
 Fmin   1  
  g R
m s Q s 
Power-Constrained Noise Optimization: (cont.)
In Saturation regime :
1 W
I D   nCox (Vgs  Vt )[(Vgs  Vt ) // LE sat ]
2 L
2  Vgs  Vt Vod
 WLC ox vsat Esat  where vsat  n Esat and  
1  2 LE sat LEsat
The power consumption is
2
PD  VDD I D  VDDWLCox vsat Esat
1 
1   / 2   W   W 
Let g m    C
2   n ox
Vod     n ox L od    g do
 C V
 (1   )  L   
3 VDD vsat Esat Po  2
Po  and Qs 
2  Rs PD 1  
2
    Qopt 
 F  Fmin   1   can be expressed in terms of  and PD
 g m Rs   Qs 
Power-Constrained Noise Optimization: (cont.)

Po  2 7
if   1 and  2  (1  c ) [1  ]
PD 5 4
Po  2
substituting into Q s 
PD 1  

5 3 
QsP  c [1  1  2 (1  ) ]  4
 c 5
Actually,
QsP is insensitive to the parameter c,

but is sensitive to the ratio of .
5
Power-Constrained Noise Optimization: (cont.)
Brief Summary :
1.  and  may change owing to hot carrier effects,
while their ratio may vary much less.
2. QsP  3.5  5.5 may be reasonable invariant.
3. Let Q sP  4.5, the width of the optimum device is
3 1 1
WoptP  
2  L Cox Rs QsP 3 L Cox Rs
(note : L is the channel length)
5. For 50  system, WoptP  250 um - GHz.
6. With a device of width WoptP , the noise figure obtained
  
within the power constraint is FminP  1  2.4  .
  T 
Design Procedure under Power Constraint Conditions:

1. To determine WoptP (eq.58);

2. Then bias the device with current allowed by the power
constraint;
3. After setting the bias current, check out the value of ωT.
4. Select the value of source degenerating inductance Ls
for input (noise) matching;
5. Compute the expected noise figure with FminP (eq.59);
6. Since
1  gm 
Zin  s(Ls  L g )   Ls  ωT L s (at resonance)
s Cgs  C gs 

Adding sufficient inductance Lg in series with the gate

to bring the input loop into resonance at the desired
operating frequency.
Design Factors to figure out:

1. Original paper by D.K. Shaeffer and Thomas H. Lee,

“ A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier”, IEEE
JSSC, vol.32, no.5, May 1997, pp.745-759.
2. By a 0.6-um CMOS process for a GPS system.
3. NF=3.5 dB; S21 = 22 dB;
4. OIP3 = 12.7 dBm;
(note : OP1dB + 10 dB ≒ OIP3)
5. (Output) P1dB = 0 dBm

6. PD (first-stage) = 7.5 mW at 1.5 V  ID = 5 mA

7. PD (second-stage) = 22.5 mW  for drive 50-Ω load.

Design Examples :
AC GND

Inductive load
(resonator + filtering)
Bias resistor

Current Mirror
Cascode:
1. Isolation
2. Less miller Cgd.

Source degenerator
Blocking cap. (both impedance /noise
Resonator to
matching purpose.)
make the
Positive resistance
input impedance
* but not a real resistor.
is purely resistive.
Design Examples : (cont.)
•Cascode Amplifier:

[Ideal case]

One-stage CG Amplifier Cascode Amplifier

Sizing Effects of the Cascoding Device:

•Features:  Higher input resistance;

 Larger transconductance;
 Superior high-frequency response.

•Sizing effects:  as size ↑ , the gain ↓ (trade-off)

 parasitic source capacitance of cascoding
device raises up it’s own internal noise.

•Suggested device structure:  so called “merged dual-gate”

structure.
 Comparisons between Single-end and Differential Configurations:

1. Drawback of Single-end Configuration :

 non-avoidable source bonding wire (inductive) effect;
2. For equal total power consumption :
 NF of differential > NF of single-end
3. For equal NF :
 Power of differential ~ 2 x Power of single-end
4. Common-mode noise rejection by “differential configuration”.
Design Examples:

•A Simple Differential LNA:

 Design Examples: (cont.) •Note: keep all transistors
operated in saturation!!
•A Complicated Differential LNA:

Current re-use Coupled cap.

for the core and for buffer inputs.
the buffer stage.
Inductive loads
of amplifier
A start-up •With a
transistor common-mode
bias feedback loop.

Source degenerator
(matching, linearity
enhancement)
Linearity and Large-Signal Performance:

•LNA must maintain linear operation when

 as receiving a weak signal, and
 as in the presence of a strong interfering signal.
(large dynamic range)

•Desensitization (or blocking) :

 signal (small) + interference (large)

•Cross-modulation:
 signal (small) + interference (large and modulated)
(distortion due to the large voltage swing)
Desensitization ( Blocking):

y (t )  1 x (t )   2 x 2 (t )   3 x 3 (t )
Let x(t )  A1 cos 1t  A2 cos 2t

3 3
y (t )  (1 A1   3 A13   3 A1 A22 ) cos 1t  
4 2
if A1  A2
3
y (t )  (1   3 A22 ) A1 cos 1t  
2
in general ,  3 is negative. Sometimes, it makes
3
(1   3 A22 )  0  blocking 
2
Cross Modulation:

y (t )  1 x(t )   2 x 2 (t )   3 x 3 (t )
Let x(t )  A1 cos 1t  A2 (1  m cos mt ) cos 2t
 [ 調變訊號 ]
if A1  A2
3 2 m2 m2
y (t )  [1 A1   3 A1 A2 (1   cos 2mt  2m cos mt )] cos 1t  
2 2 2
where the amplitute is modulated!
Nonlinearity : (intermodulation phenomenon, two-tone test)
Let i(VDC  v)  c 0  c1v  c 2 v 2  c3 v3
Consider two sinusoidal input signals of equal amplitude
but slightly different frequency (Two - tone test)
v  A[cos(1t )  cos(2t )]
<< Harmonic terms>>
Substituting v back to i( ), we have
i(VDC  v)  [c 0  c2 A2 ] DC
9
 [c1A  c3 A3 ][cos(1t )  cos(2t )] Fundamental
4
c2 A 2
[ ][cos(21t )  cos(22t )] Double-freq.
2
c3 A3
[ ][cos(31t )  cos(32t )] Triple-freq.
4
 Nonlinearity : (cont.)

Let i(VDC  v)  c 0  c1v  c 2 v 2  c3 v 3

Consider t wo sinusoidal input signals of equal amplitude
but slightly different frequency (Two - tone test)
v  A[cos(1t )  cos(2t )]
Substituti ng v back to i( ), we also have << Inter-modulated terms>>
c2 A 2
i(VDC  v)    [ ][cos(1  2 )t  cos(1  2 )t ]
2
3
 [ c3 A3 ][cos(1  22 )t  cos(1  22 )t  cos(21  2 )t  cos(21  2 )t ]
4
Input-referred third-order interception point (IIP3):

Let
3 4 c1
c1 A  c3 A3  2
A 
4 3 c3
A2  voltage square
A2 2 c1 1
IIP3  
2 Rs 3 c3 Rs
Pout plotted with Power measurement:

Output power
(dB) P1dB

10~15 dB 3rd order

Intercept
Slope = 1

Slope = 3
Input power
(dB)
IIP3
Methods for Estimating IP3:

•Simulation with tools either by

 transient simulation  FFT  Pout vs. Pin plot
 harmonic balance simulation (frequency domain)

•Two-tone testing:
 with a spectrum to read out the power levels of
inter-modulation terms.

•Three-point method: (by DC+0, ±V)

 see below.
IIP3 vs. Gain:

Let the transconductance g(v) is

g(v)  c1  2c2 v  3c3v 2
 g (0)  c1

  g (V )  c1  2c2V  3c3V 2
 g (V )  c  2c V  3c V 2
 1 2 3

4V 2  g ( 0) 
IIP3   
Rs  g (V )  g (V )  2 g (0) 
Bias dependent IP3:

There is a “sweet point” of lowest IIP3 with different

bias current for a transistor.

In the narrowband LNA architecture, the input voltage is multiplied

by the Q of the input circuit before appearing between gate and
source. Hence,

4V 2  g ( 0) 
IIP3  2  g (V )  g (Vd )  2 g (0) 
Qs Rs  
Improvement of Linearity by a pair of parallel transistors:

RFOUT

RFIN RFIN
M1 ≠ M2
Spurious-free dynamic range (SFDR):
Definition: the signal-to-noise ratio corresponding to the input
amplitude at which an undesired product (here, the third-order
IM power) just equals the noise power.

Output power
(dB)
Slope = 1
Slope = 3

Input power
SFDR
(dB)

Output
Noise level
 OIP3  N o
Pi  (because of the slope  3)
3
SFDR: (cont.)
Let N oi is the input - referred noise power (in dB).
where N oi  10 log10 ( F  kTf )
According to this figure, SFDR  (OIP3 - Po )  N o
Since
3Po  OIP3  N o
Output power 
(dB) 2 2
ΔPo SFDR  [OIP3  N o ]  [ IIP3  N oi ]
3 3

3ΔPo=OIP3-No

ΔPi Input power

SFDR
(dB)
IIP3
Output
Noise level
[the end]