Digital Integrated Circuit Design & Latches and Flip Flops: Unit: 3

Noida Institute of Engineering and Technology,
Greater Noida
Digital Integrated Circuit Design &
Latches and Flip Flops
Unit: 3
Integrated Circuits
REC – 501A NEHA
ECE
ECE, B.Tech ASSISTANT
5th Sem PROFESSOR
08/08/20 NEHA REC- 501A (INTEGRATED CIRCUITS) UNIT- 3 1

Contents
• Syllabus by University
• Course Objective
• Unit Objective
• Course Outcome
• CO-PO & CO-PSO Mapping
• Prerequisite and Recap
• Introduction to Integrated Circuits
• Basics of digital CMOS design
• Combinational MOS Logic circuits
• Sequential MOS Logic circuits

Contents
• YouTube Video Links

• Nptel Video Links
• Daily Quiz 1-5
• Weekly Assignment
• MCQs
• University Old Question Papers
• Expected Questions
• Summary
• References

Syllabus by University

Course Objectives
The intended objectives of this course are given as follows:

1.To design various circuits based on non-linear applications of OP-Amp.
2.To design active filters.
3.To design CMOS circuits and apply them in digital applications.
4.To apply the knowledge of 555 -timer IC for various applications
5.To apply the basic concepts of OP-Amp and its applications.

Unit Objective
Mapping With
Name of Unit Objective of Topic
CO
To design CMOS circuits and

Digital Integrated
apply them in digital
Circuit Design CO3
applications.

Course Outcomes
At the end of this course students will able to:

1.Design various circuits based on non-linear applications of OP-Amp.
2.Capable of designing active filters.
3.Design CMOS circuits and apply them in digital applications.
4.Apply the knowledge of 555 -timer IC for various applications
5.Apply the basic concepts of OP-Amp and its applications.

CO-PO & CO-PSO Mapping
Enter correlation levels 1, 2 or 3 as defined below:

1: Slight (Low) 2: Moderate (Medium) 3: Substantial (High)
It there is no correlation, put “-”
Course PO PO PO PSO PSO PSO

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9
Outcome 10 11 12 1 2 3
REC501A.1 3 1 2 1 1 - - - - 1 - 3 3 2 3
REC501A.2 3 3 3 3 1 2 - - 2 - - 2 2 2 3
REC501A.3 3 3 3 3 1 2 - - 2 - - 2 2 2 2
REC501A.4 3 2 3 3 1 2 - - 2 - - 2 2 2 3
REC501A.5 3 3 3 3 1 2 - 3 2 2 - 2 2 1 2
Average 3 2.4 2.8 2.6 1 2 - 3 2 1.5 - 2.2 2.2 1.8 2.6

Prerequisite and Recap
1. A class on logic design, spanning combinational and sequential

logic.
2. A class on analog electronic circuits; transistor-level circuit design.

Introduction to Integrated Circuits
• Integrated circuits (IC):

A circuit which integrate both active and passive elements with their
interconnection on a single chip of silicon. All the active and passive
elements are available on single crystal.
Typical IC packages IC packages placed on circuit board

Levels of Integration:
• SSI (Small Scale integration): up to 100 components
• MSI (Medium Scale integration): from 100 to 103 components
• LSI (Large Scale integration): from 103 to 105 components
• VLSI (Very Large Scale integration): from 105 to 106 components
• ULSI (Ultra Scale integration): from 106 to 109 components.

Advantages
• Chip area and weight of the circuit reduces.
• The cost of the circuit decreases due to production in bulk amount.
• After integration, response time of the circuit decreases and the
speed of the device increases.
• Maintenance is easier.
• Percentage yield increases.
IC’s are being used in a number of electronic applications such as

in the field of audio and radio communication, medical electronics ,
instrumentation and control etc.
Basics of Digital CMOS Design
Types of logic Circuits:

Combinational MOS Logic
Circuits (CO3)

Basics of Digital CMOS Design:
The Combinational logic circuits, or gates, perform Boolean operations

on multiple input variables and determine the outputs as Boolean
functions of the inputs.
Logic circuits can be represented as a multiple-input, single-output
system is shown in figure
Figure: Generic combinational logic circuit.

.

CMOS Technology
• Complementary MOS, or CMOS, needs both PMOS and NMOS

FET devices for their logic gates to be realized.
• The concept of CMOS was introduced in 1963 by Frank Wanlass
and Chi-Tang Sah of Fairchild
 did not become common until the 1980’s as NMOS
microprocessors were dissipating as much as 50W and
alternative design techniques were needed
• CMOS still dominates digital IC design today

MOSFET Transistors
 Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are the

transistors most widely used in integrated circuits today
 The name is due to:
 the structure of the device - a sandwich of a metal conductor, an
oxide insulator, and a semiconductor substrate
 the way it works - an electric field controls the flow of current
through the device
• Although early MOSFET transistors used metal for the first layer,
current ones use a poly-silicon material
• A conductive material with somewhat more resistance than a normal
conductor and is easier to fabricate.
N-Channel MOSFET Transistors
• With no voltage between the

gate terminal and the substrate,
there are two junctions between
the two N regions and the P
region.
• This acts like two oppositely
connected diodes, and no
current can flow between source
and drain.

N-Channel MOSFET Transistors
• Application of a positive voltage

between the gate terminal and the
substrate creates an electric field
that drives holes out of the region
under the gate, creating a channel
of N-type material that connects
the source and drain terminals.
• Current is due to electron
movement in the N-channel.

P-Channel MOSFET Transistors
• The P and N regions are

reversed from the N-Channel
device.
• Application of a voltage on the
gate terminal that is negative
relative to the substrate creates a
P channel beneath the gate and
charge flow is due to hole • gvh
movement.

MOSFET Circuit Symbols
• The following symbols are used to represent MOSFET transistors in

circuit diagrams:
normally on normally off

• The following simplified symbols are used to represent MOSFET

transistors in most CMOS circuit diagrams:
negative voltage

• The gate of a MOS transistor controls the flow of the current

between the drain and the source.
• The MOS transistor can be viewed as a simple ON/OFF switch.

• Series behavior of MOS transistors
nMOS: 1 = ON
pMOS: 0 = ON
Series:
both must be ON

• Parallel behavior of MOS transistors
nMOS: 1 = ON
pMOS: 0 = ON
Parallel:
either can be ON

Complementary MOSFETS (CMOS)
N-Channel and P-Channel transistors can be fabricated on the same

substrate as shown below
.

CMOS Logic Families

CMOS Logic Families
• 74-series (commercial) parts

are designed for
temperatures between 0°C
and 70°C.
• 54-series (military) parts are

designed for operation
between -55°C and 125°C.
• the ’00 NAND gate is the

smallest logic-design
building block in each family
• the ‘138 is a MSI part (~15

NAND gates)

CMOS Logic Families
• A CMOS load is one that requires the output to sink and source very
little DC current.
 20 µA for HC/HCT
 50 µA for VHC/VHCT
• A TTL load can consume much more sink and source current.
 up to 4 mA from and HC/HCT output
 8 mA from a VHC/VHCT output
• CMOS outputs maintain an output voltage within 0.1V of the supply

rails, 0 and VCC.
 a worst-case VCC=4.5V is used for the table; hence, VOHminC =
4.4V

Properties of NMOS and CMOS Logic Gates
• No current flows through the gate unless the input signal is changing
High input impedance
High fan-out
• Sandwich structure of MOS transistor creates capacitor between the

gate and substrate
High input capacitance
Slows transition time
Limits fan-out or switching speed
• NMOS dissipates power in low output state
• CMOS gate only dissipates power when it is changing state,

The faster a CMOS gate switches the more power it dissipates, so
there is a tradeoff between speed and power.
Why CMOS is Better?
• Low DC Power Consumption.

• Abrupt & well defined Voltage transfer Characteristic.
• Noise Immunity due to Low impedance between logic levels and
Supply/Gnd.
• Symmetry between Tfall & Trise.
• High Density: Si real estate → Yield → Cost.
• Highly Integrated → Active & High input Impedance →
Composition equality .
• No real trade off between the above.

Static vs. Dynamic CMOS Design
Static
Each gate output have a low resistive path to either VDD or GND.
Dynamic
Relies on storage of signal the value in a capacitance requires high
impedance nodes.

NMOS Logic
• Negative charge carriers (electrons)

• Positive biasing voltage at gate

CMOS Logic
• Transistors come in complementary pairs

CMOS Inverter
CMOS gates are built around the technology of the basic CMOS
inverter:
Vdd
PMOS
in out
in out
NMOS
Symbol Circuit

Basic CMOS Logic Technology
• Based on the fundamental inverter

circuit at right
Vdd
• Transistors (two) are enhancement s
g
mode MOSFETs PMOS
d
• N-Channel with its source
in out
grounded d
• P-Channel with its source g

NMOS
s
connected to +V
• Input: gates connected together
• Output: drains connected

CMOS Inverter - Operation
When input A is grounded (logic 0), the

N-Channel MOSFET is unbiased, and
therefore has no channel enhanced within
itself. It is an open circuit, and therefore
leaves the output line disconnected from Charge
ground.
At the same time, the P-Channel MOSFET Open

is forward biased, so it has a channel
enhanced within itself, connecting the
output line to the +VDD supply. This pulls
the output up to +VDD (logic 1).

When input A is at +VDD (logic 1),

the P-channel MOSFET is off and VDD
VDD
the N-channel MOSFET is on, thus
Open
pulling the output down to ground
Out
(logic 0). Thus, this circuit
correctly performs logic inversion,
A
and at the same time provides Discharge
active pull-up and pull-down,

according to the output state.

Since the gate is essentially an

open circuit it draws no Vout
current, and the output voltage VDD
will be equal to either ground

or to the power supply voltage,
depending on which transistor
VDD Vin
is conducting.
Indeterminant range

a) Circuit schematic for a CMOS inverter
b) Simplified operation model with a high input applied
c) Simplified operation model with a low input applied

• The figure shows the two modes
of static operation with the circuit
and simplified models
• Logic 1 (a) and (b)
• Logic 0 (c) and (d)
• Notice that VH = 5V and VL =
0V, and that ID = 0A which

means that there is no static
power dissipation.

CMOS Inverter Operation
Summarizing:
•When vI is pulled high (VDD), the PMOS inverter is turned off, while
the NMOS is turned on pulling the output down to GND.
•When vI is pulled low (GND), the NMOS inverter is turned off,
while the PMOS is turned on pulling the output up to VDD.

• The two modes of capacitive discharging and charging that
contribute to propagation delay

• While the fan-out of CMOS gates is affected by current limits, the fan-
out of CMOS gates driving CMOS gates is enormous since the input
currents of CMOS gates is very low.
• Why are the input currents low?
• On the other hand the high capacitance of CMOS gate inputs means
that the capacitive load on a gate driving CMOS gates increases with
fan-out.
• This increased capacitance limits switching speeds and is a far
more significant limit on the maximum fan-out.

Fan-Out in CMOS Circuits

Complementary CMOS
• Complementary CMOS logic gates

•pMOS pull-up network
•nMOS pull-down network
•a.k.a. static CMOS
Pull-up Pull-up ON pMOS

pull-up
OFF network
inputs
Pull-down Z (float) 1 output
OFF
nMOS
Pull-down 0 X pull-down
network
ON (crowbar)

Complementary CMOS
To build a logic gate we need to build two switch networks:
ASSASA

Conduction Complement
• Complementary CMOS gates always

produce 0 or 1
• Ex: NAND gate
• Series nMOS: Y=0 when both

inputs are 1
Y
• Thus Y=1 when either input is 0
• Requires parallel pMOS A
• Rule of Conduction Complements
• Pull-up network is complement of
pull-down
B
• parallel → series, series → parallel

CMOS Gate Design
• Work out the values for both the

push and pull networks
• Compare them
• What is the result?

CMOS Gate Design
A 2-input CMOS NAND gate

CMOS Gate Design
• Work out the values for both

the push and pull networks
• Compare them
• What is the result?

CMOS Gate Design
• A 2-input CMOS NOR gate

CMOS Gate Design
• A 4-input CMOS NOR gate
A
B
C
D
Y

NAND and NOR are Popular
• Logical inversion comes free

 as a result an inverting gate needs smaller number of transistors
compared to the non-inverting one

• In CMOS (and in most other logic families)
 the simples gates are inverters
 the next simplest are NAND and NOR gates

Compound Gates
Lets take a look at a gate that implements a more complex function …

Compound Gates
Compound gates can do any inverting function
Example: Y  A  B  C  D
A C A C
B D B D
(a) (b)
Y  ( A  B  C)  D
C D
A B C D
A B
(c)
(d)
C D
A
A B
B
Y Y
C
A C
D
B D
(f)
(e)

Example:
O3AI: 3 OR 1 AND
Y  ( A  B  C)  D
A
B
C D
Y
D
A B C

Sequential MOS Logic Circuits
(CO3)

• The sequential logic circuits contain one or more combinational logic

blocks along with memory in a feedback loop with the logic: The
next state of the machine depends on the present state and the inputs.
• The output depends on the present state of the machine and perhaps
also on the inputs.
 Mealy machine: output depends only on the state of the machine
Moore machine: output depends on both the present state and the
inputs.

Sequential Circuit Types :

•Bi-stable circuits have two stable operating points and will remain in
either state unless perturbed to the opposite state – Memory cells,
latches, flip-flops, and registers.
•Monostable circuits have only one stable operating point, and even if
they are temporarily perturbed to the opposite state, they will return in
time to their stable operating point.
• Astable circuits have no stable operating point and oscillate between
several states – Ring oscillator

SR Latch Circuit
CMOS SR Latch: NOR Gate Version:

The NOR-based SR Latch contains the basic memory cell (back-to-
back inverters) built into two NOR gates to allow setting the state of the
latch. The gate-level symbol and CMOS NOR-based SR latch are
shown in figure.

SR Latch Circuit
Operation of NOR-based SR Latch:

•If Set goes high, M1 is turned on, forcing Q’ low which, in turn, pulls
Q high.
•If Reset goes high, M4 is turned on, Q is pulled low, and Q’ is pulled
high.
•If both Set and Reset are low, both M1 and M4 are off, and the latch
holds its existing state indefinitely.
•If both Set and Reset go high, both Q and Q’ are pulled low, giving an
indefinite state. Therefore, R=S=1 is not allowed.

SR Latch Circuit
Depletion Load nMOS SR Latch: NOR Version:

A depletion load version of the NOR-based SR latch is shown figure.
Functionally it is the same as CMOS version.
The latch is a ratio circuit. Low side conducts dc current, causing higher
standby power than CMOS version.

SR Latch Circuit
CMOS SR Latch: NAND Gate Version:

The NAND-based SR Latch contains the basic memory cell (back-to-
back inverters) built into two NAND gates to allow setting the state of
the latch. The gate-level symbol and CMOS NAND-based SR latch are
shown in figure.

SR Latch Circuit
Operation of NAND-based SR Latch: The circuit responds to

active low S and R inputs: If S goes to 0 (while R = 1), Q goes high,
pulling Q’ low and the latch enters Set state. If R goes to 0 (while S =
1), Q’ goes high, pulling Q low and the latch is Reset. Hold state
requires both S and R to be high. S = R = 0 if not allowed, it would
result in an indeterminate state.

SR Latch Circuit
Depletion Load nMOS SR Latch: NAND Version :

A depletion load version of the NAND-based SR latch is shown figure.
Functionally it is the same as the CMOS version.

Clocked Latch and Flip Flop Circuits
Clocked SR Latch: NOR Version:

•The clocked NOR-based SR latch, contains the basic memory cell built
into two NOR gates to allow setting the state of the latch with a clock
added as shown in figure.
•The latch is responsive to inputs S and R only when CK is high.
•When CK is low, the latch retains in its current state.

Clocked Latch and Flip Flop Circuits
• CMOS AOI implementation of clocked NOR-based SR latch is

shown in figure. Only 12 transistors required.
• When CK is low, two series legs in N tree are open and two parallel
transistors in P tree are ON,thus retaining state in the memory cell.
• When CK is high, the circuit becomes simply a NOR-based CMOS
latch which will respond to inputs S and R.
CMOS D Latch And Edge-triggered Flip Flops
CMOS D-Latch Implementation:

•A D-latch is implemented, at the gate level, by simply utilizing a
NOR-based S-R latch, connecting D to input S, and connecting D’ to
input R with an inverter as shown in figure.
•When CK goes high, D is transmitted to output Q (and D’ to Q’).
•When CK goes low,the latch retains its previous state.

• The D latch implemented with TG switches is shown in figure.

• The input TG is activated with CK while the latch feedback loop TG
is activated with CK’.
• Input D is accepted when CK is high.
• When CK goes low, the input is open-circuited and the latch is set
with the prior data D.

• A schematic view of the D-Latch can be obtained using simple

switches in place of the TG’s as shown in figure.
• When CK = 1, the input switch is closed allowing new input data
into the latch.
• When CK = 0, the input switch is opened and the feedback loop
switch is closed, setting the latch.
• CMOS D Flip-Flop Figure shows a D Flip-Flop, constructed by
cascading two D-Latch circuits from the previous slide: Master latch
is positive level sensitive (receives data when CK = 1).

• Slave latch is negative level sensitive (receives data Qm when CK =

0), the circuit is negative edge triggered.
• Master latch receives input D until the CK falls from 1 to 0, at which
point it sets that data in the master latch and sends it through to the
output Qs.

Youtube Links
•Problem on Complex CMOS logic gates

https://www.youtube.com/watch?v=CoTR3bwtW_c
•CMOS Logic Family | Digital Electronics

https://www.youtube.com/watch?v=ZkrAn5vNmig&t=1578s
•Complement of a Function
https://www.youtube.com/watch?v=Pn_KVcH0Jqw
•CMOS Inverter
https://www.youtube.com/watch?v=fi3wjPzob_o
https://www.youtube.com/channel/UCSU9QsujYox4WDoIETBmV
aA

Nptel Links
• CMOS introduction
https://nptel.ac.in/courses/108/106/108106069/
• CMOS inverter construction

https://nptel.ac.in/courses/108/106/108106158/

Daily Quiz-1
• The switching of MOS gates can be improved by using CMOS.

a) True
b) False
• A family of logic devices dsigned for extremely high speed

applications is called
a) NMOS
b) PMOS
c) ECL
d) TTL
Daily Quiz-2
1. CMOS inverter circuit has a pair of transitors which are

a) Two PMOS
b) TWo BJTs
c) Two NMOS
d) Two complementary CMOS

2. Threshold Voltages of PMOS and NMOS in CMOS invertr are
a) Equal in magnitude
b) Opposite in magnitude
c) Infinite in magnitude
d) Zero
3. Complementary CMOS of inverter source is connected to its

a) Source
b) Drain
c) Gate
d) Body

Daily Quiz-3
1. Each switch is modeled by a finite ON resistance, which is the

a) Gate drain resistance
b) Source drain resistance
c) Source gate resistance
d) Source body resistance

2. The CMOS inverter can be represented by
a) Complementary resistors
b) Complementary inductors
c) Complementary capacitors
d) Complementary switches


Daily Quiz-4
1. Latches consist of
a) Inductors
b) Inverters
c) Timing generators
d) Frequency generators
2. In SR flip flop input labeled “S” stand for

a) Systematic
b) Static
c) Set
d) Stable
3. D flip flops tracks the

a) Input
b) Output
c) Source
d) Ground

Daily Quiz-5
1. In SR Flip flops, set reset circuitary is made up of

a) NMOS
b) PMOS
c) CMOS
d) BiCMOS

2.In master slave circuit, to maintain most of circuit charge we relay on
a) Bypass Capacitor
b) Node Capacitor
c) Input Capacitor
d) Load Capacitor
.
3.D flip flop consist of
a) One inverter
b) Two inverters
c) One buffer
d) Two buffers


Weekly Assignments
1. Find truth table and CMOS realization of following gates :

1. AND-OR-INVERT (AOI); F = (AB + CD)’
2. OR-AND-INVERT (OAI); F = [(A + B) (C + D)]’
2. Design a CMOS HALF SUBTRACTOR with input A and B and

output difference (D) and Borrow ().

3. Give the CMOS Logic Circuit that realizes the function of three
inputs ODD Parity Checker specifically the Output is to be high
when an odd number(l or 3) of the input is high.
Weekly Assignments
4. Discuss the features of CMoS circuit. Discuss the effect of Fan-in

and Fan-out on propagation delay in CMOS digital logic circuit.
5. Derive the formula for VIH, and VOL, of CMOS inverter.
6. Find the expression of y in terms of A and B and hence the truth table
for the circuit shown in Figure.


MCQs
• If p-transistor is conducting and has small voltage between source and

drain, then the it is said to work in
a) linear region
b) saturation region
c) non saturation resistive region
d) cut-off region
• If both the transistors are in saturation, then they act as

a) current source
b) voltage source
c) divider
d) buffer

MCQs
• CMOS inverter has ______ regions of operation

a) three
b) four
c) two
d) five
• If n-transistor conducts and has large voltage between source and

drain, then it is said to be in _____ region
a) linear
b) saturation
c) non saturation
d) cut-off

MCQs
• In the region where inverter exhibits gain, the two transistors are in
_______ region
a) linear
b) cut-off
c) non saturation
d) saturation
• If βn = βp, then Vin is equal to

a) Vdd
b) Vss
c) 2Vdd
d) 0.5Vdd

MCQs
• Mobility depends on
a) transverse electric field
b) Vg
c) Vdd
d) Channel length
• In CMOS inverter, transistor is a switch having

a) infinite on resistance
b) finite off resistance
c) buffer
d) infinite off resistance
• CMOS inverter has ______ output impedance

a) low
b) high
MCQs
• Increasing fan-out, ______ the propogation delay

a) increases
b) decreases
c) does not affect
d) exponentially decreases
• 12. Fast gate can be built by keeping

a) low output capacitance
b) high on resistance
c) high output capacitance
d) input capacitance does not affect speed of the gate
• Input resistance of CMOS inverter is

a) high
b) low
Old Question Papers
• Right Click on page attached above and then click Acrobat Document Object and then
click open OR Simply double click on it.

Old Question Papers

Old Question Papers

Expected Questions for University Exam
1. Sketch the logic gate symbolic representation of

• SR Flip flop using CMOS with NAND GATES.
• JK Flip Flop using CMOS with NAND GATES.
2. Identify the OUTPUT expression (Z) for given CMOS
inputs ODD Parity Checker specifically the Output is to be high
4. What is PDN and PUN ?

5. Sketch the CMOS logic circuit realization of the expression
Y  A( B  C )  DE
6. Draw the D Flip-Flop using CMOS.

7. Give CMOS implementation of a clocked SR Flip-Flop and explain
its working.
8. Derive the formula for VIL and VIH of CMOS inverter.
9. Give two different CMOS realization of the exclusive –OR function
in which the PDN and PUN are dual networks.

10. CMOS realization of Following gates:

Y  ( A  B )(C  D )
• AND-OR-INVERT (AOI)
• Y  ( A  B)(C  D)
OR-AND-INVERT (OAI)
11. Sketch the Logic gate symbolic representation of clocked SR Flip
Flop using nand gates. Also sketch its CMOS circuit implementation
and explain its operation.
12. Draw the D-Flip Flop using CMOS. Also draw and explain its
Master slave configuration.
inputs ODD Parity Checker specifically the Output. is to be high

Summary
• This presentation focuses on the implementation of digital logic

circuits using CMOS technology.
• Today, CMOS technology is best suited for realizing digital systems.
• Reasons for its popularity are – 1. small size 2. ease of fabrication 3.
low power operations 5. relatively simpler manufacturing process
6.high impedance allowing it to be used as a charge storage device
etc.
• All these features have contributed to high levels of integration and
correspondingly sophisticated circuit designs.

References
1. M.Morris Mano, “Digital Design”, 5th Edition, Pearson.

2.Michael Jacob, “Applications and Design with Analog Integrated
Circuits”, PHI, 2nd Edition.
3.Ram Gayakwad, “Op-Amps and Linear Integrated Circuits, Pearson,
4th Edition, 2000


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Noida Institute of Engineering and Technology,

08/08/20 NEHA REC- 501A (INTEGRATED CIRCUITS) UNIT- 3 1

08/08/20 NEHA REC- 501A (INTEGRATED CIRCUITS) UNIT- 3 2

• YouTube Video Links

08/08/20 NEHA REC- 501A (INTEGRATED CIRCUITS) UNIT- 3 3

08/08/20 NEHA REC- 501A (INTEGRATED CIRCUITS) UNIT- 3 4

The intended objectives of this course are given as follows:

08/08/20 NEHA REC- 501A (INTEGRATED CIRCUITS) UNIT- 3 5

To design CMOS circuits and

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At the end of this course students will able to:

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Enter correlation levels 1, 2 or 3 as defined below:

Course PO PO PO PSO PSO PSO

08/08/20 NEHA REC- 501A (INTEGRATED CIRCUITS) UNIT- 3 8

1. A class on logic design, spanning combinational and sequential

08/08/20 NEHA REC- 501A (INTEGRATED CIRCUITS) UNIT- 3 9

• Integrated circuits (IC):

Typical IC packages IC packages placed on circuit board

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IC’s are being used in a number of electronic applications such as

Types of logic Circuits:

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The Combinational logic circuits, or gates, perform Boolean operations

Figure: Generic combinational logic circuit.

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• Complementary MOS, or CMOS, needs both PMOS and NMOS

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 Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are the

• With no voltage between the

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• Application of a positive voltage

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• The P and N regions are

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• The following symbols are used to represent MOSFET transistors in

normally on normally off

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• The following simplified symbols are used to represent MOSFET

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• The gate of a MOS transistor controls the flow of the current

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• Series behavior of MOS transistors

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• Parallel behavior of MOS transistors

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N-Channel and P-Channel transistors can be fabricated on the same

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• 74-series (commercial) parts

• 54-series (military) parts are

• the ’00 NAND gate is the

• the ‘138 is a MSI part (~15

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• CMOS outputs maintain an output voltage within 0.1V of the supply

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• Sandwich structure of MOS transistor creates capacitor between the

• NMOS dissipates power in low output state

• CMOS gate only dissipates power when it is changing state,

• Low DC Power Consumption.