COA - Chapter # 6

INPUT/OUTPUT
CHAPTER # 6 Computer Organization & Architecture

External Devices
S H E H E R YAR MALI K
 Human readable
 Screen, printer, keyboard
 Machine readable
 Monitoring and control
 Communication
 Modem
 Network Interface Card (NIC)
Chapter # 6 Computer Organization & Architecture 2

Input/Output Problems
 Wide variety of peripherals

 Delivering different amounts of data
 At different speeds
 In different formats
 All slower than CPU and RAM
 Need I/O modules

Input/Output Module
 Interface to CPU and Memory

 Interface to one or more peripherals

Generic Model of I/O Module

External Device Block Diagram

I/O Module Function
 Control & Timing

 CPU Communication
 Device Communication
 Data Buffering
 Error Detection

I/O Steps
 CPU checks I/O module device status

 I/O module returns status
 If ready, CPU requests data transfer
 I/O module gets data from device
 I/O module transfers data to CPU
 Variations for output, DMA, etc.

I/O Module Diagram

I/O Module Decisions
 Hide or reveal device properties to CPU

 Support multiple or single device
 Control device functions or leave for CPU
 Also O/S decisions
 e.g. Unix treats everything it can as a file

Input Output Techniques
 Programmed I/O
 Interrupt driven I/O
 Direct Memory Access (DMA)

Three Techniques for Input of a Block of Data

Programmed I/O
 CPU has direct control over I/O

 Sensing status
 Read/write commands
 Transferring data
 CPU waits for I/O module to complete operation
 Wastes CPU time

Programmed I/O - Detail
 CPU requests I/O operation

 I/O module performs operation
 I/O module sets status bits
 CPU checks status bits periodically
 I/O module does not inform CPU directly
 I/O module does not interrupt CPU
 CPU may wait or come back later

I/O Commands
 CPU issues address

 Identifies module (& device if >1 per module)
 CPU issues command
 Control - telling module what to do
 e.g. spin up disk
 Test - check status
 e.g. power? Error?
 Read/Write
 Module transfers data via buffer from/to device

Addressing I/O Devices
 Under programmed I/O data transfer is very like

memory access (CPU viewpoint)
 Each device given unique identifier
 CPU commands contain identifier (address)

I/O Mapping
 Memory mapped I/O

 Devices and memory share an address space
 I/O looks just like memory read/write
 No special commands for I/O
 Large selection of memory access commands available
 Isolated I/O
 Separate address spaces
 Need I/O or memory select lines
 Special commands for I/O
 Limited set

Interrupt Driven I/O
 Overcomes CPU waiting

 No repeated CPU checking of device
 I/O module interrupts when ready

Interrupt Driven I/O Basic Operation
 CPU issues read command

 I/O module gets data from peripheral whilst CPU
does other work
 I/O module interrupts CPU
 CPU requests data
 I/O module transfers data

Simple Interrupt Processing

CPU Viewpoint
 Issue read command

 Do other work
 Check for interrupt at end of each instruction cycle
 If interrupted
 Save context (registers)
 Process interrupt
 Fetch data & store

Changes in Memory and Registers for an Interrupt

Design Issues
 How do you identify the module issuing the

interrupt?
 How do you deal with multiple interrupts?
 i.e. an interrupt handler being interrupted

Identifying Interrupting Module
 Multiple Interrupt Lines

 Different line for each module
 Limits number of devices
 Software poll
 CPU asks each module in turn
 Slow
 Daisy Chain or Hardware poll
 Interrupt Acknowledge sent down a chain
 Module responsible places vector on bus
 CPU uses vector to identify handler routine
 Bus Master
 Module must claim the bus before it can raise interrupt
 e.g. PCI & SCSI
Multiple Interrupts
 Each interrupt line has a priority

 Higher priority lines can interrupt lower priority lines
 If bus mastering only current master can interrupt

Direct Memory Access
 Interrupt driven and programmed I/O require active

CPU intervention
 Transfer rate is limited
 CPU is tied up
 DMA is the answer

DMA Function
 Additional Module (hardware) on bus

 DMA controller takes over from CPU for I/O

Typical DMA Module Diagram

DMA Operation
 CPU tells DMA controller

 Read/Write
 Device address
 Starting address of memory block for data
 Amount of data to be transferred
 CPU carries on with other work
 DMA controller deals with transfer
 DMA controller sends interrupt when finished

DMA Transfer Cycle Stealing
 DMA controller takes over bus for a cycle

 Transfer of one word of data
 Not an interrupt
 CPU does not switch context
 CPU suspended just before it accesses bus
 i.e. before an operand or data fetch or a data write
 Slows down CPU but not as much as CPU doing
transfer

DMA Configurations
 Single Bus, Detached DMA controller

 Each transfer uses bus twice
 I/O to DMA then DMA to memory
 CPU is suspended twice

DMA Configurations
 Single Bus, Integrated DMA controller

 Controller may support >1 device
 Each transfer uses bus once
 DMA to memory
 CPU is suspended once

DMA Configurations
 Separate I/O Bus

 Bus supports all DMA enabled devices
 Each transfer uses bus once
 DMA to memory
 CPU is suspended once
Intel 8237A DMA Controller
 Interfaces to 80x86 family and DRAM

 When DMA module needs buses it sends HOLD signal to processor
 CPU responds HLDA (hold acknowledge)
 DMA module can use buses
 E.g. transfer data from memory to disk
1. Device requests service of DMA by pulling DREQ (DMA request) high
2. DMA puts high on HRQ (hold request),
3. CPU finishes present bus cycle (not necessarily present instruction) and puts
high on HDLA (hold acknowledge). HOLD remains active for duration of DMA
4. DMA activates DACK (DMA acknowledge), telling device to start transfer
5. DMA starts transfer by putting address of first byte on address bus and
activating MEMR; it then activates IOW to write to peripheral. DMA
decrements counter and increments address pointer. Repeat until count
reaches zero
6. DMA deactivates HRQ, giving bus back to CPU

8237 DMA Usage of Systems Bus

Fly-By
 While DMA using buses, processor is idle

 Processor using bus, DMA is idle
 Known as fly-by DMA controller
 Data does not pass through and is not stored in DMA
chip
 8237 contains four DMA channels
 Programmed independently
 Any one active
 Numbered 0, 1, 2, and 3

I/O Channels
 I/O devices getting more sophisticated

 e.g. 3D graphics cards
 CPU instructs I/O controller to do transfer
 I/O controller does entire transfer
 Improves speed
 Takes load off CPU
 Dedicated processor is faster

I/O Channel Architecture

The Evolution of the I/O Function
 Programmed I/O
 The CPU directly controls a peripheral device
 Simple microprocessor controlled devices
 I/O Module
 A controller or I/O module is added
 The CPU uses programmed I/O without interrupts
 CPU somewhat divorced from the details of external device interfaces
 Interrupt Driven
 Now interrupts are employed
 The CPU need not spend time waiting for an I/O operation to be performed
 thus increasing efficiency
 DMA
 The I/O module is given direct access to memory via DMA
 It can now move a block of data to or from memory without involving the CPU,
except at the beginning and end of the transfer

The Evolution of the I/O Function
 I/O Channel
 The I/O module is enhanced to become a processor in its own right,
with a specialized instruction set tailored for I/O
 The CPU directs the I/O processor to execute an I/O program in
memory
 The I/O processor fetches and executes these instructions without CPU
intervention
 I/O Processor
 The I/O module has a local memory of its own
 A large set of I/O devices can be controlled, with minimal CPU
involvement

Parallel and Serial I/O
 Parallel interface
 multiple lines connecting the
peripheral
 multiple bits are transferred
simultaneously
 Serial interface
 Only one line used to transmit
data
 bits must be transmitted one at a
time

Point-to-Point vs Multipoint interface
 Connection between an I/O module in a computer

system and external devices can be either:
 point-to-point
 multiport
 Point-to-point interface
 provides a dedicated line between the I/O module and the
external device
 On small systems (PCs, workstations) typical point-to-point links
include those to the keyboard, printer, and external modem
 Multipoint external interfaces
 used to support external mass storage devices (disk and tape
drives) and multimedia devices (CD-ROMs, video, audio)

Thunderbolt
 Most recent and fastest peripheral connection technology to become

available for general-purpose use
 Developed by Intel with collaboration from Apple
 The technology combines data, video, audio, and power into a single high-
speed connection for peripherals such as hard drives, RAID arrays, video-
capture boxes, and network interfaces
 Provides up to 10 Gbps throughput in each direction and up to 10 Watts of
power to connected peripherals
 A Thunderbolt-compatible peripheral interface is considerably more
complex than a simple USB device
 First generation products are primarily aimed at the professional-
consumer market such as audiovisual editors who want to be able to move
large volumes of data quickly between storage devices and laptops
 Thunderbolt is a standard feature of Apple’s MacBook Pro laptop and iMac
desktop computers

Thunderbolt in a Computer Configuration

Thunderbolt Protocol Layers

InfiniBand
 Recent I/O specification aimed at the high-end server

market
 First version was released in early 2001
 Standard describes an architecture and specifications for
data flow among processors and intelligent I/O devices
 Has become a popular interface for storage area
networking and other large storage configurations
 Enables servers, remote storage, and other network
devices to be attached in a central fabric of switches and
links
 The switch-based architecture can connect up to 64,000
servers, storage systems, and networking devices
InfiniBand Switch Fabric

InfiniBand Links and Data Throughput Rates

zEnterprise 196
 Introduced in 2010
 IBM’s latest mainframe computer offering
 System is based on the use of the z196 chip
 5.2 GHz multi-core chip with four cores
 Can have a maximum of 24 processor chips (96 cores)
 Has a dedicated I/O subsystem that manages all I/O operations
 Of the 96 core processors, up to 4 of these can be dedicated for I/O use,
creating 4 channel subsystems (CSS)
 Each CSS is made up of the following elements:
 System assist processor (SAP)
 Hardware system area (HSA)
 Logical partitions
 Subchannels
 Channel path
 Channel

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INPUT/OUTPUT

CHAPTER # 6 Computer Organization & Architecture

Chapter # 6 Computer Organization & Architecture 2

 Wide variety of peripherals

Chapter # 6 Computer Organization & Architecture 3

 Interface to CPU and Memory

Chapter # 6 Computer Organization & Architecture 4

Chapter # 6 Computer Organization & Architecture 5

Chapter # 6 Computer Organization & Architecture 6

 Control & Timing

Chapter # 6 Computer Organization & Architecture 7

 CPU checks I/O module device status

Chapter # 6 Computer Organization & Architecture 8

Chapter # 6 Computer Organization & Architecture 9

 Hide or reveal device properties to CPU

Chapter # 6 Computer Organization & Architecture 10

Chapter # 6 Computer Organization & Architecture 11

Chapter # 6 Computer Organization & Architecture 12

 CPU has direct control over I/O

Chapter # 6 Computer Organization & Architecture 13

 CPU requests I/O operation

Chapter # 6 Computer Organization & Architecture 14

 CPU issues address

Chapter # 6 Computer Organization & Architecture 15

 Under programmed I/O data transfer is very like

Chapter # 6 Computer Organization & Architecture 16

 Memory mapped I/O

Chapter # 6 Computer Organization & Architecture 17

 Overcomes CPU waiting

Chapter # 6 Computer Organization & Architecture 18

 CPU issues read command

Chapter # 6 Computer Organization & Architecture 19

Chapter # 6 Computer Organization & Architecture 20

 Issue read command

Chapter # 6 Computer Organization & Architecture 21

Chapter # 6 Computer Organization & Architecture 22

 How do you identify the module issuing the

Chapter # 6 Computer Organization & Architecture 23

 Multiple Interrupt Lines

 Each interrupt line has a priority

Chapter # 6 Computer Organization & Architecture 25

 Interrupt driven and programmed I/O require active

Chapter # 6 Computer Organization & Architecture 26

 Additional Module (hardware) on bus

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 CPU tells DMA controller

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 DMA controller takes over bus for a cycle

Chapter # 6 Computer Organization & Architecture 30

 Single Bus, Detached DMA controller

Chapter # 6 Computer Organization & Architecture 31

 Single Bus, Integrated DMA controller

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 Separate I/O Bus

 Interfaces to 80x86 family and DRAM

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 While DMA using buses, processor is idle

Chapter # 6 Computer Organization & Architecture 36

 I/O devices getting more sophisticated

Chapter # 6 Computer Organization & Architecture 37

Chapter # 6 Computer Organization & Architecture 38