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Electrical

Engineering

Islamabad

EEE241
Digital Logic Design
Lecture No. 3
Dr. Riaz Hussain
Assistant Professor
Department of Electrical Engineering
COMSATS Institute of Information Technology, Islamabad
Review
• Define the following:
– Closure, Associative law, Commutative law, Identity element, Inverse and Distributive
• What is the difference between ordinary algebra and Boolean algebra w.r.t.
distributive law
• What is a postulate?
• What is “Duality” and what is its utility?
• What is involution?
• What is operator precedence rule for Boolean algebra?
• How can you convert a Boolean expression in SoP canonical form to PoS canonical
form?
• What are the standard SoP and PoS forms?
• What is the truth table for XOR and XNOR gates
• What are the digital logic families?
• Define “fan out” and “propagation delay”?

07/08/2020 Dr. Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 2


Outline
• Introduction to gate-level minimization
• The map method
• Four variable K-Map
• PoS simplification
• Don’t care condition
• NAND and NOR implementation
• Other two level implementations
• XOR function
• HDL
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 3
Must Reading
• Chapter No. 3: Gate-Level Minimization

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 4


Introduction
“Gate-level minimization is the design task of finding an optimal
gate-level implementation of the Boolean functions describing a
digital circuit”

• Manually difficult for several inputs


• Logic synthesis tools can do it very efficiently and quickly,
BUT
• Designer must understand underlying mathematical description

“will enable you to execute a manual design of simple circuits,


preparing you for skilled use of modern design tools”

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 5


The Map Method
• Truth table is unique, but algebraic expressions can be many
• Rules for simplification of an algebraic expressions are intuitive and not
straight forward
• Karnaugh map or K-map:
– simple, straightforward procedure for minimizing Boolean functions
– Diagram made of square
– Each square represents one (1) min term
– Enables visualize all possible ways of expressing a Boolean algebraic
function
– Can give simplest expression
• Simplest expression?
– Minimum number of terms and with the smallest possible number of
literals in each term
– expression produces a circuit diagram with a minimum number of
gates and the minimum number of inputs to each gate
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 6
Karnaugh Map
• Adjacent Squares
– Number of squares = number of combinations
• Each square represents a minterm
• 2 Variables  4 squares
• 3 Variables  8 squares
• 4 Variables  16 squares
– Each two adjacent squares differ in one variable
• Two adjacent minterms can be combined together
Note: adjacent squares horizontally and vertically NOT diagonally
Example: F = x y + x y’
= x ( y + y’ )
=x
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 7
Two Variable K-Map
• Example
x y F Minterm
m0 m1
0 0 0 0 m0 xy
1 0 1 0 m1 xy m2 m3
2 1 0 0 m2 xy
3 1 1 1 m3 xy
y
y x 0 1

0 0 0 xy xy

x 0 1 1 xy xy
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 8
… continued 2

Two Variable K-Map


• Example
x y F Minterm
m0 m1
0 0 0 0 m0 xy
1 0 1 1 m1 xy m2 m3
2 1 0 1 m2 xy
3 1 1 1 m3 xy
y
y x 0 1
F  x yxyxy
0 1 0 xy xy
( x  x) y x ( y  y )
x 1 1 1 xy xy
F  yx
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 9
Three-variable Map
x y z Minterm m0 m1 m3 m2
0 0 0 0 m0 x y z
m4 m5 m7 m6
1 0 0 1 m1 xyz
2 0 1 0 m2 x yz
yz
3 0 1 1 m3 x yz x 00 01 11 10
4 1 0 0 m4 xyz
0 x yz x yz x yz x yz
5 1 0 1 m5 xyz
6 1 1 0 m6 xyz 1 xyz xyz xyz xyz

7 1 1 1 m7 xyz
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 10
Three-variable Map
m0 m1 m3 m2
• Example
m4 m5 m7 m6
x y z F Minterm
yz
0 0 0 0 0 m0 x y z x 00 01 11 10
1 0 0 1 0 m1 x y z 0 x yz x yz x yz x yz
2 0 1 0 1 m2 x y z 1 xyz xyz xyz xyz
3 0 1 1 1 m3 x y z
y
4 1 0 0 1 m4 x y z
5 1 0 1 1 m5 x y z 0 0 1 1

6 1 1 0 0 m6 x y z x 1 1 0 0
z
7 1 1 1 0 m7 x y z
F  xy  xy
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 11
Three-variable Map
m0 m1 m3 m2
• Example
m4 m5 m7 m6
x y z F Minterm
yz
0 0 0 0 0 m0 x y z x 00 01 11 10
1 0 0 1 0 m1 x y z 0 x yz x yz x yz x yz
2 0 1 0 0 m2 x y z 1 xyz xyz xyz xyz
3 0 1 1 1 m3 x y z
y
4 1 0 0 1 m4 x y z
5 1 0 1 0 m5 x y z 0 0 1 0

6 1 1 0 1 m6 x y z x 1 0 1 1
z
7 1 1 1 1 m7 x y z Extra
F  xz  yz  xy
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 12
Three-variable Map y
• Example
x y z F Minterm 0 1 1 0
0 0 0 0 0 m0 x y z x 0 1 1 0
1 0 0 1 1 m1 x y z z
F  x yzx yzxyzxyz
2 0 1 0 0 m2 x y z
3 0 1 1 1 m3 x y z x z ( y  y) x z ( y  y)
4 1 0 0 0 m4 x y z xz xz
z
5 1 0 1 1 m5 x y z y
6 1 1 0 0 m6 x y z 0 1 1 0
7 1 1 1 1 m7 x y z x 0 1 1 0
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD
z Lecture-03 13
Three-variable Map
m0 m1 m3 m2
• Example
m4 m5 m7 m6
x y z F Minterm
yz
0 0 0 0 1 m0 x y z x 00 01 11 10
1 0 0 1 0 m1 x y z 0 x yz x yz x yz x yz
2 0 1 0 1 m2 x y z 1 xyz xyz xyz xyz
3 0 1 1 0 m3 x y z
y
4 1 0 0 1 m4 x y z
5 1 0 1 1 m5 x y z 1 0 0 1

6 1 1 0 1 m6 x y z x 1 1 0 1
z
7 1 1 1 0 m7 x y z
F  z  xy
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 14
Four-variable Map
m0 m1 m3 m2
w x y z Minterm
0 0 0 0 0 m0 wx yz
m4 m5 m7 m6
1 0 0 0 1 m1 wxyz m12 m13 m15 m14
2 0 0 1 0 m2 wx yz
3 0 0 1 1 m3 wx yz m8 m9 m11 m10
4 0 1 0 0 m4 wxyz
m5
yz
5 0 1 0 1 wxyz
6 0 1 1 0 m6 wxyz wx 00 01 11 10
7 0 1 1 1 m7 wxyz 00 w x yz w x yz w x yz w x yz
8 1 0 0 0 m8 wx y z
9 1 0 0 1 m9 wx y z 01 w xyz w xyz w xyz w xyz
10 1 0 1 0 m10 wx y z
11 1 0 1 1 m11 wx y z 11 wxyz wxyz wxyz wxyz
12 1 1 0 0 m12 wx y z
13 1 1 0 1 m13 wx y z
m14
10 wx yz wx yz wx yz wx yz
14 1 1 1 0 wx y z
15 1 1 1 1 m15
wx y z
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 15
Four-variable
yz Map
• Example wx 00 01 11 10
w x y z F Minterm 00 w x yz w x yz w x yz w x yz
0 0 0 0 0 1 m0 wxyz
1 0 0 0 1 1 m1 wxyz
01 w xyz w xyz w xyz w xyz
2 0 0 1 0 1 m2 wx yz 11 wxyz wxyz wxyz wxyz
3 0 0 1 1 0 m3 wx yz
m4
10 wx yz wx yz wx yz wx yz
4 0 1 0 0 1 wxyz
5 0 1 0 1 1 m5 wxyz
6 0 1 1 0 1 m6 wxyz
y
7 0 1 1 1 0 m7 wxyz
8 1 0 0 0 1 m8 wx y z
1 1 0 1
9 1 0 0 1 1 m9 wx y z 1 1 0 1
x
10 1 0 1 0 0 m10 wx y z 1 1 0 1
w
11 1 0 1 1 0 m11 wx y z 1 1 0 0
12 1 1 0 0 m12 wx y z
1 z
13 1 1 0 1 1 m13 wx y z
F  y  wz  xz
14 1 1 1 0 1 m14 wx y z
15 1 1 1 1 0 m15 wx y z
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 16
Four-variable Map
•Example
Simplify: F = A’ BC’ + B’ C D’ + A’ B C D’ + A B’ C’
C

B
A
D

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 17


Four-variable Map
•Example
Simplify: F = A’ B’C’ + B’ C D’ + A’ B C D’ + A B’ C’
C
1 1

B
A
D

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 18


Four-variable Map
•Example
Simplify: F = A’ B’ C’ + B’ C D’ + A’ B C D’ + A B’
C’
C
1
B
A
1
D

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 19


Four-variable Map
•Example
Simplify: F = A’ B’ C’ + B’ C D’ + A’ B C D’ + A B’ C’
C

1
B
A
D

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 20


Four-variable Map
•Example
Simplify: F = A’ B’ C’ + B’ C D’ + A’ B C D’ + A B’ C’
C

B
A
1 1
D

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 21


Four-variable Map
•Example
Simplify: F = A’ B’ C’ + B’ C D’ + A’ B C D’ + A B’ C’
C
1 1 1
1 B
A 1 1 1
D

F  B D  B C  A CD

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 22


Five-variable Map
DE D DE D
BC 00 01 11 10 BC 00 01 11 10
00 m0 m1 m3 m2 00 m16 m17 m19 m18
01 m4 m5 m7 m6 01 m20 m21 m23 m22
C C
11 m12 m13 m15 m14 11 m28 m29 m31 m30
B B
10 m8 m9 m11 m10 10 m24 m25 m27 m26

E E
A=0 A=1

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 23


Five-variable Map

A=0

A=1

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 24


Implicants

Implicant:
C
Gives F = 1
1
1 1 1
B
1 1 1
A
1
D

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 25


Prime Implicants
Prime Implicant:
Can’t grow beyond C
this size
1
1 1 1
B
1 1 1
A
1
D

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 26


Essential Prime Implicants
8 Implicants, 5 Prime implicants, 4 Essential prime implicants
Essential Prime Not essential
Implicant: C
No other choice
1
1 1 1
B
1 1 1
A
1
D
To ensure that a minimum solution is found, select essential prime
implicants first. Then find a minimum set of prime implicants that
cover the remaining 1's on the map.
07/08/2020 27
Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03
Product of Sums Simplification
y y
w x y z F F
0 0 0 0 0 1 0 w
1 1 0 1 z F
1 0 0 0 1 1 0
1 1 0 1 x
2 0 0 1 0 1 0 x z
3 0 0 1 1 1 1 0 1
0 1 w
4 0 1 0 0 1 0 1 1 0 0
5 0 1 0 1 1 0 z F  y w z x z
6 0 1 1 0 1 0
7 0 1 1 1 0 1 y
8 1 0 0 0 1 0 F  y z w x y
9 1 0 0 1 1 0 1 1 0 1
x F  y zwx y
10 1 0 1 0 0 1 1 1 0 1
11 1 0 1 1 0 1 1 1 0 1
12 1 1 0 0 1 0 w y
1 1 0 0
13 1 1 0 1 1 0 z
14 1 1 1 0 1 0
z w F
x
15 1 1 1 1 0 1 y
F  ( y  z )  (w  x  y )
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 28
Don’t-Care Condition
A {
1 if a quarter is deposited
•Example
0 otherwise

B {0 1 if a dime is deposited
otherwise

C {
1 if a nicle is deposited
0 otherwise

A B C $ Value You can only


0 0 0 $ 0.00
drop one coin at
0 0 1 $ 0.05
0 1 0 $ 0.10 a time.
0 1 1 Not possible
1 0 0 $ 0.25
1 0 1 Not possible Used as
1 1 0 Not possible “don’t care”
1 1 1 Not possible
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 29
Don’t-Care Condition
•Example A

Logic F
B
Circuit

A B C F F ( A, B, C )   (1, 4)
0 0 0 0
0 0 1 1 d ( A, B, C )   (3, 5, 6, 7)
0 1 0 0
0 1 1 x
1 0 0 1 Don’t care
1 0 1 x what value F
1 1 0 x
1 1 1 x
may take
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 30
Don’t-Care Condition
•Example A

B F

0 1 x 0
A 1 x x x
C
F  A B C  AB C
F  AC
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 31
Don’t-Care Condition
• Example F (w, x, y, z) = ∑(1, 3, 7, 11, 15)
d (w, x, y, z) = ∑(0, 2, 5)
x=0 x=1 x=0
y y
x 1 1 x x x
x=1
x 1 0 x 0
x x
1 0 0 0
w w
1 0 0 0
z z

F  yzwz F  zwy
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 32
Tabulation Method
Input: f on as a set of minterms
Output: f on as a set of
1. All Essential Prime Implicants
2. As Few Prime Implicants as Possible

Finding as few Prime Implicants as Possible


is an NP-Hard Problem!!!!!
• Reduces to the “Set Covering” Problem for Unate Functions
Unate function – a constant or is represented by a SOP using
either uncomplemented or complemented literals for each
variable
• Reduces to the “Minimum Cost Assignment” Problem for Binate
Functions (ex. EXOR)
This is 2-Level (SOP) Optimization (Minimization)
Tabulation Method
• STEP 1:
– Convert Minterm List (specifying f on) to Prime Implicant List
• STEP 2:
– Choose All Essential Prime Implicants
– If all minterms are covered
HALT
Else
GO To STEP 3
• STEP 3:
– Formulate the Reduced Cover Table Omitting the rows/cols of EPI
– If Cover Table can be Reduced using Dominance Properties, Go To Step 2
– Else Must Solve the “Cyclic Cover” Problem
1) Use Exact Method (exponentially complex)
2) Use Heuristic Method (possibly non-optimal result)

NOTE: “Quine-McCluskey” Refers to Using a “Branch and Bound” Heuristic


NOTE: “Petrick’s Method” is Exact Technique – Generates all Solutions
Allowing the Best to be Used
Tabulation Method – STEP 1
1. Partition Prime Implicants (or minterms) According to Number of 1’s

2. Check Adjacent Classes for Cube Merging Building a New List

3. If Entry in New List Covers Entry in Current List – Disregard Current


List Entry

4. If Current List = New List


HALT
Else
Current List  New List
New List  NULL
Go To Step 1
STEP 1 - EXAMPLE

f on = {m0, m1, m2, m3, m5, m8, m10, m11, m13, m15} =  (0, 1, 2, 3, 5, 8, 10, 11, 13, 15)

Minterm Cube
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
8 1 0 0 0
3 0 0 1 1
5 0 1 0 1
10 1 0 1 0
11 1 0 1 1
13 1 1 0 1
15 1 1 1 1
STEP 1 - EXAMPLE

f on = {m0, m1, m2, m3, m5, m8, m10, m11, m13, m15} =  (0, 1, 2, 3, 5, 8, 10, 11, 13, 15)

Minterm Cube Minterm Cube


0 0 0 0 0  0,1 0 0 0 -
1 0 0 0 1  0,2 0 0 - 0
2 0 0 1 0  0,8 - 0 0 0
8 1 0 0 0  1,3 0 0 - 1
3 0 0 1 1  1,5 0 - 0 1
5 0 1 0 1  2,3 0 0 1 -
10 1 0 1 0  2,10 - 0 1 0
11 1 0 1 1  8,10 1 0 - 0
13 1 1 0 1  3,11 - 0 1 1
15 1 1 1 1  5,13 - 1 0 1
10,11 1 0 1 -
11,15 1 - 1 1
13,15 1 1 - 1
STEP 1 - EXAMPLE

f on = {m0, m1, m2, m3, m5, m8, m10, m11, m13, m15} =  (0, 1, 2, 3, 5, 8, 10, 11, 13, 15)

Minterm Cube Minterm Cube Minterm Cube


0 0 0 0 0  0,1 0 0 0 -  0,1,2,3 0 0 - -
1 0 0 0 1  0,2 0 0 - 0  0,8,2,10 - 0 - 0
2 0 0 1 0  0,8 - 0 0 0  2,3,10,11 - 0 1 -
8 1 0 0 0  1,3 0 0 - 1 
3 0 0 1 1  1,5 0 - 0 1
5 0 1 0 1  2,3 0 0 1 - 
10 1 0 1 0  2,10 - 0 1 0 
11 1 0 1 1  8,10 1 0 - 0 
13 1 1 0 1  3,11 - 0 1 1 
15 1 1 1 1  5,13 - 1 0 1
10,11 1 0 1 - 
11,15 1 - 1 1
13,15 1 1 - 1
STEP 1 - EXAMPLE

f on = {m0, m1, m2, m3, m5, m8, m10, m11, m13, m15} =  (0, 1, 2, 3, 5, 8, 10, 11, 13, 15)

Minterm Cube Minterm Cube Minterm Cube


0 0 0 0 0  0,1 0 0 0 -  0,1,2,3 0 0 - - PI=A
1 0 0 0 1  0,2 0 0 - 0  0,8,2,10 - 0 - 0 PI=C
2 0 0 1 0  0,8 - 0 0 0  2,3,10,11 - 0 1 - PI=B
8 1 0 0 0  1,3 0 0 - 1 
3 0 0 1 1  1,5 0 - 0 1 PI=D
5 0 1 0 1  2,3 0 0 1 - 
10 1 0 1 0  Question: Can this be
2,10 - 0 1 0 
11 1 0 1 1  8,10 1 0 - 0  done on a CCM? How
13 1 1 0 1   modified?
3,11 - 0 1 1
15 1 1 1 1 
5,13 - 1 0 1 PI=E
10,11 1 0 1 - 
11,15 1 - 1 1 PI=F
13,15 1 1 - 1 PI=G

f on = {A,B,C,D,E,F,G} = {00--, -01-, -0-0, 0-01, -101, 1-11, 11-1}


STEP 2 – Construct Cover Table

• PIs Along Vertical Axis (in order of # of literals)


• Minterms Along Horizontal Axis

0 1 2 3 5 8 10 11 13 15
A x x x x
B x x x x
C x x x x
D x x
E x x
F x x
G x x

NOTE: Table 4.2 in book is incomplete


STEP 2 – Finding the Minimum Cover
• Extract All Essential Prime Implicants, EPI
• EPIs are the PI for which a Single x Appears in a Column
0 1 2 3 5 8 10 11 13 15
A x x x x
B x x x x
C x x x x
D x x
E x x
F x x
G x x

• C is an EPI so: f on={C, ...}


• Row C and Columns 0, 2, 8, and 10 can be Eliminated
Giving Reduced Cover Table
• Examine Reduced Table for New EPIs
STEP 2 – Reduced Table
Distinguished Column
0 1 2 3 5 8 10 11 13 15
A x x x x
B x x x x
C x x x x Essential row
D x x
E x x
F x x
G x x

1 3 5 11 13 15
•The Row of an EPI is an
A x x Essential row
B x x
D x x •The Column of the Single x in
E x x
F x x the Essential Row is a
G x x Distinguished Column
Row and Column Dominance
• If Row P has x’s Everywhere Row Q Does
Then Q Dominates P if P has fewer x’s

• If Column i has x’s Everywhere j Does


Then j Dominates i if i has fewer x’s

• If Row P is equal to Row Q and Row Q does not cost more than Row P,
eliminate Row P, or if Row P is dominated by Row Q and Row Q Does
not cost more than Row P, eliminate Row P

• If Column i is equal to Column j, eliminate Column i or if Column i


dominates Column j, eliminate Column i
STEP 3 – The Reduced Cover Table
• Initially, Columns 0, 2, 8 and 10 Removed
1 3 5 11 13 15
A x x
B x x
D x x
E x x
F x x
G x x

• No EPIs are Present


• No Row Dominance Exists
• No Column Dominance Exists
• This is Cyclic Cover Table
• Must Solve Exactly OR Use a Heuristic
The Cyclic Cover Table
• For now, we Arbitrarily Choose a PI
• Later we will Study Exact and Heuristic Methods

1 3 5 11 13 15
A x x
B x x
D x x
E x x
F x x
G x x

• Arbitrarily Choose F so: fon={C, F, ...}


This Choice May Lead to a Non-Optimal Result!!!!
• Form Reduced Cover and Go To Step 2
STEP 3 – Dominance
• Initially, Reduced Table has Columns 11 and 15
Removed
1 3 5 13
A x x
B x
D x x
E x x
G x

• G is Dominated by E
• B is Dominated by A
• Form Reduced Cover Table and Go To Step 2
STEP 2 – The Reduced Cover
• Initially, Table has Rows G and B Removed

1 3 5 13
A x x
D x x
E x x
• Secondary EPIs – A and E
• All Columns Covered
• Eliminate D
• fon={C, F, A, E}
Result Check

cd cd
ab 00 01 11 10 ab 00 01 11 10
00 1 1 1 1 00 1 1 1 1

01 1 01 1

11 1 1 11 1 1

10 1 1 1 10 1 1 1

Initial Minterm List Final Result


fon = {m0, m1, m2, m3, m5, m8, m10, m11, m13, m15} f on={A, C, E, F}
=  (0, 1, 2, 3, 5, 8, 10, 11, 13, 15)
Universal Gates
• One Type
– Use as many as you need (quantity), but one type only.
• Perform Basic Operations
– AND, OR, and NOT
• NAND Gate
– NOT-AND functions
– OR function can be obtained from AND by Demorgan’s
• NOR Gate
– NOT-OR functions (AND by Demorgan’s)

Digital circuits are frequently constructed with NAND or NOR gates rather
than with AND and OR gates.
NAND and NOR gates are easier to fabricate with electronic components and
are the basic gates used in all IC digital logic families.
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 49
Universal Gates
• NAND Gate
– NOT:
A F=A

– AND:
A F=A•B
B
– OR:
DeMorgan’s

A
F=A+B
B
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD BCE-3 Lecture-03 50
Universal Gates
• NOR Gate
– NOT: A F=A

– OR: A
B F=A+B

– AND:
DeMorgan’s

A
F=A•B
B
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 51
NAND & NOR Implementation
• Two-Level Implementation
A A A
B B B
F F F
C C C
D D D

A A
B B
F F
C C
D D

B
F
C

D
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 52
NAND & NOR Implementation
• Two-Level Implementation
A A A
B B B
F F F
C C C
D D D

A A
B B
F F
C C
D D

B
F
C

D
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 53
NAND & NOR Implementation
• Multilevel NAND Implementation
C C
D D
B B
A A
B F B F
C C

C
D
B
A
B F
C

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 54


NAND & NOR Implementation
• Multilevel NOR Implementation
A A
B B
A A
B F B F

C C
D D

A
B
A
B F

C
D

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 55


Gate Shapes
• AND

• OR

• NAND

• NOR

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 56


Other Implementations
• AND-OR-Invert

• OR-AND-Invert

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 57


Implementations Summary
• Sum Of Products:
– AND-OR
– AND-OR-Invert = AND-NOR = NAND-AND
• Products Of Sums
– OR-AND
– OR-AND-Invert = OR-NAND = NOR--OR

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 58


Exclusive-OR
• XOR
F=xy=xy+xy
x x

F F

y y
• XNOR
F=xy=x y=xy+xy

x x

F F

y y
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 59
Exclusive-OR
• Identities
–x0=x x y XOR
–x1=x 0 0 0
–xx=0 0 1 1
1 0 1
–xx=1 1 1 0
–xy=xy=xy
• Commutative & Associative
–xy=yx
–(xy)z=x(yz)=xyz

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 60


Exclusive-OR Functions
• Odd Function x y z XOR XNOR
0 0 0 0 1
F=xyz
0 0 1 1 0
F = ∑(1, 2, 4, 7) 0 1 0 1 0
x 0 1 1 0 1
y F 1 0 0 1 0
z
1 0 1 0 1
• Even Function 1 1 0 0 1
F=xyz 1 1 1 1 0

F = ∑(0, 3, 5, 6) yz
x 00 01 11 10
x 0 0 1 0 1
y F
z 1 1 0 1 0

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 61


Parity
1 1
0 0
1 0
0
0

1 1
0 0
1 0
0
0
1

1

Parity Parity
Generator Checker
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 62
Parity Generator
• 1 Odd Parity 1
0 0
1 1
0 0

1
Odd number of ‘1’s
• Even Parity
1 1
0 0
1 1
0 0

0
Even number of ‘1’s

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 63


Parity Checker
• 1 Odd Parity
0
1
0

Error
1
Check
• Even Parity
1
0
1
0

Error
0 Check
07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 64
Practice Problems
• 3.1, 3.3, 3.5, 3.7, 3.9, 3.15, 3.16, 3.18, 3.22, 3.28
• Convert the logic diagram of the circuit shown in Fig.
4-4 into a multiple-level NAND circuit.
z

D
C y

B
x

A w

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 65


Recommended Reading
• http
• Acknowledgement and References:
– Chapter No. 3 Digital Design with verilog By M. Mano and Ciletti
– These slides are obtained from Princess Sumaya University, Computer Engineering
Department Course 4241-Digital Logic Design

07/08/2020 Riaz Hussain (rhussain@comsats.edu.pk) CIIT-IBD-EE EEE241 DLD Lecture-03 66

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