Multipliers

PRESENTED BY:-
ADITI DOGRA
ROLL NO. 101603
 Why Multipliers?
• Used in a lot of DSP applications
 Vector product, matrix multiplication
 Convolution
 Filtering (tap filters, FIR, …)
 ...
“At least one good reason for studying multiplication
and division is that there is an infinite number of ways
of performing these operations and hence there is an
infinite number of PhDs (or expense-paid visits to
conferences in USA) to be won from inventing new forms
of multiplier”
 Multiplication Example
• Example: 12x5

Multiplicand: 1 1 0 0 12
Multiplier: 0 1 0 1 5

1 1 0 0
0 0 0 0 4 partial products
1 1 0 0
0 0 0 0

0 1 1 1 1 0 0 60

• The partial product can be generated using an

array of AND gates
 General Form
• Multiplicand: Y = (yM-1, yM-2, …, y1, y0)
• Multiplier: X = (xN-1, xN-2, …, x1, x0)

• Product:  M 1   N 1
 N 1 M 1
P    y j 2 j    xi 2i     xi y j 2i  j
 j 0   i 0  i 0 j 0
y5 y4 y3 y2 y1 y0 multiplicand
x5 x4 x3 x2 x1 x0 multiplier
x0y5 x0y4 x0y3 x0y2 x0y1 x0y0
x1y5 x1y4 x1y3 x1y2 x1y1 x1y0
x2y5 x2y4 x2y3 x2y2 x2y1 x2y0 partial
x3y5 x3y4 x3y3 x3y2 x3y1 x3y0 products
x4y5 x4y4 x4y3 x4y2 x4y1 x4y0
x5y5 x5y4 x5y3 x5y2 x5y1 x5y0
p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 product
 Dot Diagram
• Each dot represents a bit

x0

partial products

multiplier x
x15
 Outline
• Serial Multiplier
• Multiplier arrays
• Carry save adder (CSA) and multiple
operand addition
• Booth encoding
• Pipelined multipliers
• Wallace tree
 Array Multiplier

y3 y2 y1 y0

x0

x1
CSA
Array

x2

x3

CPA

p7 p6 p5 p4 p3 p2 p1 p0

A B
Sin A Cin critical path A B
A B
B Sin
= Cout Cin = Cout Cin
Cout Cin
Sout
Cout Sout Sout
Sout
 Sequential Multiplier
• Shift register
 Originally holds multiplicand
 Shifts it left for each partial product
• One bit of multiplier at a time presented to the
AND gates
2N bits
Shift Register 0
One bit of
mplier applied
Initialized w/ each cycle
mcand,
shifts it left
Adder

Register
Sequential Multiplier – Resource Requirements
• Adder: 2N-bit Register
• Registers: 2N-bit wide
• Better design:
 Shift result register to
right Adder
 Uses N AND gates
 Uses N-bit adder Shift Register

Register

Adder

Shift Register
 WALLACE TREE MULTIPLIER
• Another way to speed up multiplication.
• Adder tree built from carry-save adders.
• Performs three-to-two reductions.
• Wallace tree requires:
• [log3/2(N/2)] levels of (3,2) counters to reduce N
inputs down to 2 carry-save redundant form
outputs.
 Advantages and Disadvantages
• Faster than a simple array-multiplioer.
• Large number of adders required.
• Wallace tree’s wiring is much less regular and
more complicated.
• Wallace trees are often avoided by designers who
do not have extreme demands for multiplication
speed and for whom design complexity is a
consideration.
 Multiplier: Summary
• Goals different than addition
 In some structures, sum and carry delay equal
 Analysis more difficult : Multiple critical paths
• Different levels of optimization
 Data encoding (Booth)
 Architecture-level: Wallace Tree
 Gate-level: pipelining
 Transistor-level: equal sum, carry delays
• More to cover:
 Constant multiplication
 Floating point, precision
 REFERENCE
• “DELAY BALANCED MULTIPLIERS FOR LOW
POWER DSP CORE”(Toshiyuki Sakuta,Wai Lee
and Poras T.Balsara}
• Delay Balanced Array Multiplier

• Delay Balanced Wallace Tree Multiplier

• SPICE Simulation Results

• Conclusion