Unit-V

Comparators
 Comparator Structure

• EXCLUSIVE OR and EXCLUSIVE NOR gates may be viewed as 1-bit

comparators.

• The 74x86 XOR gate can be used as a 1-bit comparator. The active-high
output, DIFF, is asserted if the inputs are different.

• Given enough XOR gates and wide enough OR gates, comparators with any
number of input bits can be built.
 Iterative Circuits

• The circuit contains n identical modules, each of which has both primary inputs and outputs
and cascading inputs and outputs.

• The leftmost cascading inputs are called boundary inputs and are connected to fixed logic
values in most iterative circuits.

• The rightmost cascading outputs are called boundary outputs and usually provide important
information.

• Iterative circuits are well suited to problems that can be solved by a simple iterative
algorithm:

1. Set C0 to its initial value and set i to 0.

2. Use Ci and PIi to determine the values of POi and Ci+1.
3. Increment i.
4. If i < n, go to step 2.

• In an iterative circuit, the loop of steps 2–4 is “unwound” by providing a separate

combinational circuit that performs step 2 for each value of i.

• Eg: The 74x85 4-bit comparator and the 74x283 4-bit adder are MSI circuits that can be used
as the individual modules in a larger iterative circuit.
Iterative Circuits
 An Iterative Comparator Circuit

• Two n-bit values X and Y can be compared one bit at a time using a single bit EQi at each step to
keep track of whether all of the bit-pairs have been equal so far:

1. Set EQ0 to 1 and set i to 0.

2. If EQi is 1 and Xi and Yi are equal, set EQi + 1 to 1. Else set EQi+1 to 0.
3. Increment i.
4. If i < n, go to step 2.

• saves cost but delay increases due to ripple of cascading signals.

An MSI IC74x85 4- bit comparator has cascading inputs ALTBIN, AEQBIN, AGTBIN
MSI Comparator
 Comparator Conditions

• Derived from IC74x682 and 74xx Series

 VHDL Program

library IEEE; architecture vcompare_arch of vcompare

use IEEE.std_logic_1164.all; is
Begin
entity vcompare is
port ( process (A, B)
A, B: in STD_LOGIC_VECTOR (7 downto Begin
0);
EQ, NE, GT, GE, LT, LE: out STD_LOGIC EQ <= '0'; NE <= '0'; GT <= '0'; GE <= '0';
); LT <= '0'; LE <= '0';
end vcompare; if A = B then EQ <= '1'; end if;
if A /= B then NE <= '1'; end if;
if A > B then GT <= '1'; end if;
if A >= B then GE <= '1'; end if;
if A < B then LT <= '1'; end if;
if A <= B then LE <= '1'; end if;

end process;
end vcompare_arch;
 VHDL Program
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity vcompa is
port (
A, B: in UNSIGNED (7 downto 0);
C: in SIGNED (7 downto 0);
D: in STD_LOGIC_VECTOR (7 downto 0);
A_LT_B, B_GE_C, A_EQ_C, C_NEG,
D_BIG, D_NEG: out STD_LOGIC
);
end vcompa;
architecture vcompa_arch of vcompa is
begin
process (A, B, C, D)
Begin
A_LT_B <= '0'; B_GE_C <= '0'; A_EQ_C <=
'0'; C_NEG <= '0'; D_BIG <= '0'; D_NEG
<= '0';
if A < B then A_LT_B <= '1'; end if;
if B >= C then B_GE_C <= '1'; end if;
if A = C then A_EQ_C <= '1'; end if;
if C < 0 then C_NEG <= '1'; end if;
if UNSIGNED(D) > 200 then D_BIG <= '1';
end if;
if SIGNED(D) < 0 then D_NEG <= '1'; end
if;
end process;
end vcompa_arch;