MOS Field-Effect

Transistors (MOSFETs)

1
 MOSFET ( Voltage Controlled Current Device)
• MOS Metal Oxide Semiconductor
Physical Structure

• FET Field Effect Transistor

The current controlled mechanism is based on an electric field established by the
voltage applied to the control terminal – GATE

• Uni-polar Current is conducted by only one carrier

• IGFET Insulated Gate FET

• CMOSFET Complementary MOSFET

• 1930 was Known, 1960s Commercialized

1970s Most commonly used VLSI

• NMOSFET/PMOSFET n/p-channel enhancement mode MOSFET

 MOSFET
• Small Size

• Manufacturing process is simple

• Requires comparatively low power

• Implement digital & analog functions with a fewer

resistors very large scale Integrated (VLSI) circuit

• Study Includes
– Physical structure
– Operation
– Terminal characteristics
– Circuit Models
– Basic Circuit application
Figure 4.1 Physical structure of the enhancement-type NMOS
transistor:
 Device Structure
• Types “n” channel enhancement MOSFET
“p” channel enhancement MOSFET

• “n” Channel MOSFET

– Fabricated on a p-type substance that provides physical support for
the device.

– Two heavily doped n-type region are created

• n+ Source (‘S’) n- for lightly doped ‘n’ type silicon
• n+ Drain (‘D’) n+ for heavily doped ‘n’ type silicon

– Area between source & Drain

• Thin Layer of Silicon dioxide (SiO2) is grown with thickness of tox =
2-50 nanometers An excellent electrical insulator

• Metal is deposited on top of the oxide layer to form

the Gate electrode. Metal contact is made to Source
& Drain and the substrate (Body)
Figure 4.1 Physical structure of the enhancement-type NMOS
transistor

Cross-section. Typically L = 0.1 to 3 m, W = 0.2 to 100 m, and

the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.
 Device Structure
• Four terminals
– Source (S)
– Gate (G)
– Drain (D)
– Body (B)

• L Length of channel region

W Width of the substrate
tox Thickener of An oxide Layer
 Device Structure
• Metal oxide semiconductor - name is derived
from its physical structure

• Insulted – Gate FET (IGFET) – gate is

electrically insulated from the device body
– Current in gate terminal is small (10-15 A)

• Substrate forms pn junctions with the source &

drain region & is kept reversed biased all the
time

• Drain will be at a positive voltage relative to the

source, two junctions are at cutoff mode if
substrate is connected to the source. Thus Body
will have no effect on operation of the device.
 Principle of operation
• Voltage applied to the Gate controls current flow between
Source & Drain with direction from Drain to Source in
channel region

• It is a symmetrical device thus Drain & Source can be

interchanged with no change in devices characteristics
•
• With no bias gate voltage, two back-to-back diodes exist
in series between drain and source.

• No current flows even if vDS is applied. In fact the path

between Source & Drain (1012Ω) has very high resistance
Figure 4.2 The enhancement-type NMOS transistor with a
positive voltage applied to the gate. An n channel is
induced at the top of the substrate beneath the gate.
Creating a Channel for Current Flow

• Source & Drain are grounded and a positive

voltage (vGS) is applied to the gate.

• Holes are repelled-leaving behind a carrier

depletion-region.

• Depletion region is populated with the bounded

negative charges associated with the acceptor
atoms and are uncovered because the
neutralizing holes have been push downward
into the substrate.
 Channel for Current Flow
• Positive gate attracts electrons from the n+
source & drain region into the channel region.

• Due to electrons accumulated under the gate, an

‘n’ region is created & connects source & drain
region.

• Thus if voltage is applied between source &

drain, current flows due to mobile electrons
between drain & source.

• ‘n’ region forms a channel – ‘n’ channel MOSET

(NMOSFET)
 Channel for Current Flow
• An ‘n’ channel MOSFET is formed in a ‘p’ type
substrate. Known as “Inversion Layer”.

• The value of vGS that causes sufficient number of

mobile electrons to be accumulate in the
channel region to form conducting channel is
called threshold Voltage “Vt”.

• Vt for ‘n’ channel is positive & value is 0.5 to 1V

 Channel for Current Flow
• Gate & channel region form a parallel plate capacitor,
with oxide layer as the capacitor dielectric.

• Positive charge is accumulated on gate electrode &

negative charge on channel electrode.

• An electric field thus develops in the vertical direction.

• Capacitor charge controls the current flow through the

channel when a voltage vDS is applied.
• Gate Channel

Figure 4.3 An NMOS transistor with vGS > Vt and with a
small vDS applied.

The device acts as a resistance whose value is determined by vGS.

Specifically, the channel conductance is proportional to vGS – Vt’
and thus i is proportional to (v – V ) v .
 Applying a Small vDS
• vDS is applied (vDS = 50mV) causes iD to flow through induced ‘n’ channel.
– Direction is opposite to that of the flow of negative charges.
– Magnitude of iD depends upon density of electrons and in term on vGS .

• vGS ≤ Vt
– Negligible current iD as the channel has been just induced.

• vGS > Vt
– iD current increases, increases conductance of the channel & is proportional to
Excess gate voltage (vGS - Vt )

– vGS - Vt is known as Excess gate Voltage , Effective Voltage Overdrive

Voltage (VOV)

– MOSFET operatrates as a linear resistance whose value is controlled by

vGS.

– vGS above Vt enhances the channel – named Enhanced Mode operation &
enhanced type MOSFET
iD = i S, i G = 0
Figure 4.4 The iD–vDS characteristics of the MOSFET

When the voltage applied between drain and source, vDS, is kept small.
The device operates as a linear resistor whose value is controlled by vGS.
 Figure 4.5 Operation of the enhancement NMOS
transistor as vDS is increased. The induced channel
acquires a tapered shape, and its resistance increases as
vDS is increased. Here, vGS is kept constant at a value >
Vt.
The drain current iD versus the drain-to-source voltage

vDS for an enhancement-type NMOS transistor operated

Increasing vDS causes the channel to acquire a tapered shape. Eventually,

as vDS reaches vGS – Vt’ the channel is pinched off at the drain end.

Increasing vDS above vGS – Vt has little effect (theoretically, no effect) on

the channel’s shape.

Derivation of the iD–vDS characteristic of the NMOS transistor.
 Drain Current iD
• Directly Proportional to:
– Mobility of Electrons in the channel μn (μm2/V)
– Gate Capacitance per unit gate area Cox (μF/ μm)
– Width of the substrate (μm)
– Gate-Source Voltage vGS (Volts)
– Drain-Source Voltage v DS (Volts)

• Indirectly Proportional to:

– Length of the channel (μm)
 iD – vDS relationship
Troide Mode

Saturation Mode
 The p Channel MOSFET
• Fabricated on an n-type substrate with p+ regions for Drain
& Source

• Holes are the current carriers.

• vGS & vDS are negative

• Threshold voltage Vt is negative.

• Both NMOS & PMOS are utilized in Complementary MOS

or CMOS circuits
 Complementary MOS or CMOS

Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in

a separate n-type region, known as an n well. Another arrangement is also possible in

which an n-type body is used and the n device is formed in a p well. Not shown are the

connections made to the p-type body and to the n well; the latter functions as the body

terminal for the p-channel device.

Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an
arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c)
Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device
operation is unimportant.
 iD – vDS Charateristics
• Modes of operation
• Cutoff Region
– The device is cut-off when

• Triode (Saturation in BJT)

– To operate the FET in triode region we must induce a
channel by
 iD – vDS Charateristics
• In triode region the iD ~ VDS is related as

• Where we have assumed VDS to be very

small then the equation can be approx as:

• Now, the resistance rDS is given as

 2
The iD–vDS characteristics for a device with k’n (W/L) = 1.0 mA/V .
 iD – vDS Charateristics
– Modes of operation
• Saturation (Active Region in BJT)
– To Operate FET in saturation region a Channel must be induced

– Pinched-off at the drain end up by raising vDS to a value

– Or it can be re-written as
– Thus, an N-Channel enhancement MOSFET operates in saturation
region, when vGS is greater than Vt and the Drain voltage does not
fall below the gate voltage by more than Vt volts.
• The boundary region b/w the triode region & saturation
region is characterized by:
– Saturation Current is given as:
 Saturation current iD is independent of vDS voltage
which shows that iD current is a voltage controlled
current source and is dependent on vGS.

The iD–vGS characteristic for an enhancement-type NMOS transistor in saturation (Vt =

2
1 V, k’n W/L = 1.0 mA/V ).
Large-signal equivalent-circuit model of an n-channel MOSFET
 Finite Output Resistance in Saturation

Increasing vDS beyond vDSsat causes the channel pinch-off point

to move slightly away from the drain, thus reducing the effective
 Finite Output Resistance in Saturation

Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the

process technology and, for a given process, is proportional to the channel length L.
 Finite Output Resistance in Saturation

Large-signal equivalent circuit model of the n-channel MOSFET in saturation,

incorporating the output resistance ro. The output resistance models the linear

dependence of iD on vDS
Circuit symbol for the p-channel enhancement-type MOSFET.
Characteristics of PMOSFET
Triode Mode of Operation
 Characteristics of PMOSFET
Satuaration Mode of Operation
 The Roll of Substrate :
Body Effect
• Substrate for many Transistors

• Body is connected to the most negative

power supply to maintain cutoff conditions
for all the substrates to channel junctions

• Another gate
 Temperature Effects
• Vt and K’n are effected by the temperature

• Vt increases by 2mV per 10C rise in temperature

• K’n decreases with rise in temperature thus drain

current increases. The effect is dominant. Thus
ID decreases with increase in temperature
MOSFET in Power circuits
Graphical construction to determine the transfer characteristic of the
Biasing the MOSFET using a large drain-to-gate feedback resistance, RG.
Biasing the MOSFET using a constant-current source
Conceptual circuit utilized to study the operation of the MOSFET
Recap : Transfer Function
Transfer characteristic showing operation as an amplifier biased at point

Q.
Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.

The DC BIAS POINT

To Ensure Saturation-region Operation

Signal Current in Drain Terminal
Total instantaneous voltages vGS and vD
Small-signal ‘π’ models for the MOSFET
Common Source amplifier circuit

Example 4-10
Small Signal ‘T’ Model : NMOSFET
Small Signal Models

‘T’ Model
Single Stage MOS Amplifier
Amplifiers Configurations
Common Source Amplifier (CS) :Configuration
Common Source Amplifier (CS)
• Most widely used

• Signal ground or an ac earth is at the source

through a bypass capacitor

• Not to disturb dc bias current & voltages

coupling capacitors are used to pass the
signal voltages to the input terminal of the
amplifier or to the Load Resistance

• CS circuit is unilateral –
– Rin does not depend on RL and vice versa
Small Signal Hybrid “π” Model
(CS)
 Small Signal Hybrid “π” Model : (CS)

vo vo v gs
Gv   
vsig v gs vsig
Rin  RG RG
v gs  v sig
RG  Rsig
R o  ro || RD vo   g m v gs  ro || RD || RL 

vo  RG 
Gv    g m  ro || RD || RL   

v gs  RG  Rsig 
Small-signal analysis performed directly on the amplifier circuit with the MOSFET model implicitly

utilized.

vo  RG 
Rin  RG R o  ro || RD   g m  ro || RD || RL   
v gs R R 
 G sig 
 BJT / MOSFET

  ,   1
Rin  RB || r Rin  RG
Rout  ro || RC Rout  ro || RD
vo RB || r vo RG
  gm  ro || RC || RL    gm  ro || RD || RL 
vsig RB || r  Rsig vsig RG  Rsig
 Common Source Amplifier (CS)
Summary
• Input Resistance is infinite (Ri=∞)
Rin  RG
• Output Resistance = RD
R o  ro || RD

• Voltage Gain is substantial

vo  RG 
  g m  ro || RD || RL   
v gs R R 
 G sig 
 Common-source amplifier

with a resistance RS in the source lead

 The Common Source Amplifier
with a Source Resistance
• The ‘T’ Model is preferred, whenever a
resistance is connected to the source terminal.

• ro (output resistance due to Early Effect) is not included, as it

would make the amplifier non unilateral & effect
of using ro in model would be studied in Chapter
‘6’
 Small-signal equivalent circuit with ro neglected.

vg
i
1
 RS
gm
Small-signal Analysis.

Rin  RG
Ro  RD
Voltage Gain : CS with RS

vo vo v gs vi
Gv    
vsig v gs vi vsig
vo   g m v gs  RD || RL 
1
gm vi
v gs  vi 
1 1  g R
 RS m S
gm
RG
vi  vsig
RG  Rsig
vo  RG  g m  RD || RL  
 Gv   
 
vsig R R  1 g R
 G sig  m S 
 Common Source Configuration with Rs
• Rs causes a negative feedback thus
improving the stability of drain current of
the circuit but at the cost of voltage gain

• Rs reduces id by the factor

– (1+gmRs) = Amount of feedback

• Rs is called Source degeneration

resistance as it reduces the gain
Small-signal equivalent circuit directly on Circuit
A common-gate amplifier based on the circuit
 Common Gate (CG) Amplifier
• The input signal is applied to the source

• Output is taken from the drain

• The gate is formed as a common input &

output port.

• ‘T’ Model is more Convenient

• ro is neglected
A small-signal equivalent circuit
A small-signal Analusis : CG

vi vi 1
Rin   
ii g m vi g m

Rout  RD
A small-signal Analusis : CG

vo vo vi
Gv   
vsig vi vsig
vo  g m vi  RD || RL 
1
Rin gm vsig
vi  vsig  vsig 
Rin  Rsig 1 1  g m Rsig
 Rsig
gm
vo g  R || RL 
Gv   m D
vsig 1  g m Rsig
Small signal analysis directly on circuit
The common-gate amplifier fed with a current-signal input.
 Summary : CG

4. CG has much higher output Resistance

5. CG is unity current Gain amplifier or a Current Buffer
6. CG has superior High Frequency Response.
A common-drain or source-follower amplifier.
Small-signal equivalent-circuit model
Small-signal Analysis : CD
(a) A common-drain or source-follower amplifier :output resistance Rout of the source

follower.

 1  1
Rout  ro ||   
 gm  gm
(a) A common-drain or source-follower amplifier. : Small-signal analysis performed directly on the

circuit.
Common Source Circuit (CS)
Common Source Circuit (CS) With RS
Common Gate Circuit (CG)

Current Follower
Common Drain Circuit (CD)

Source Follower
Summary & Comparison
 Quiz No 4
27-03-07

• Draw/Write the Following:

BJT MOSFET
Types npn pnp nMOS pMOS
Symbols
‘π’ Model
T Model
gm
Re/rs
rπ/rg
Problem 5-44
SOLUTION : DC Analysis
 SOLUTION : DC Analysis

5  I E  3.3  0.7  I B 100  0

IE
5  I E  3.3  0.7  100  0
(1   )
IE
5  0.7
IE   1mA
100
3.3 
IB 101

Vt 25
re    25
I E 1.0

gm = 40mA/V
Solution Small Signal Analysis
Solution Small Signal Analysis
Solution Small Signal Analysis : Input Resistance

ib

vb

Rin

vb (   1)vb
Rin    (   1) re  RC || RL 
ib ie
 Solution Small Signal Analysis : Output Resistance
Itest

IE
IRC

IE/(1+ß)

Rout

Vtest Vtest
Rout  I RC 
I test RC RC  re 
Rsig
 R 
Vtest (1   )
Rout    RC || re  sig 
Vtest Vtest Rsig (1   ) 
I test  I RC  I E I  Vtest RC

Rsig
RC  re 
(1   )

E re 
Rsig (1   )
re 
(1   )
 Solution Small Signal Analysis : Voltage Gain

+
vo vo veb vi
veb   
vsig veb vi vsig
-
-

vo
+ Vo
  g m  RC || RL 
+
veb
vi

-
 Solution Small Signal Analysis : Voltage gain

+
vo vo veb vi
veb   
vsig veb vi vsig
-

vo
+
  g m  RC || RL 
veb
vi

-
veb re

vi re   RC || RL 
 Solution Small Signal Analysis : Voltage Gain
vo vo veb vi
  
vsig veb vi vsig

vo
  g m  RC || RL 
veb
+ veb re

vi vi re   RC || RL 
-
vi Rin

vsig Rin  Rsig
(1   ) re  RC || RL 

(1   ) re  RC || RL   Rsig
Rin  (   1) re  RC || RL 
 Solution Small Signal Analysis : Voltage Gain
vo vo veb vi vo
     g m  RC || RL 
vsig veb vi vsig veb

veb re vi Rin
 
vi re   RC || RL  vsig Rin  Rsig

vo re Rin
  g m(RC||RL )  
vsig re  (RC || RL ) Rin  Rsig
vo (RC||RL ) Rin
 g m re  
vsig re  (RC || RL ) Rin  Rsig

vo (RC||RL ) Rin
  
vsig re  (RC || RL ) Rin  Rsig
 Solution Small Signal Analysis : Voltage Gain

vo vo vi
 
vsig vi vsig

 RC || RL 
-

vo

Vo
+

+
vi re   RC || RL 
vi

vi Rin
-

vsig Rin  Rsig

vo (RC||RL ) Rin
 
vsig re  (RC || RL ) Rin  Rsig
Problem
Small Signal Model MOSFET : CD
Solution Small Signal Analysis

1/gm

D
gmvsg
Solution Small Signal Analysis : Input Resistance

1/gm

Ig=0

D
gmvsg

Rin

Rin  
 Solution Small Signal Analysis : Output Resistance
Itest

1/gm

ID
IRD
0V
Vtest
IG=0 D

gmvsg

Rout

Vtest Vtest
Rout  I RD 
I test RD
Vtest 1
I test  I RC  I D ID 
Vtest Rout 
Vtest Vtest
 RD ||
 gm
1
RD 1 / g m
gm
 Solution Small Signal Analysis : Voltage Gain

vo vo vsg vi
vsg   
1/gm
vsig vsg vi vsig
-

-
vo
+
  g m  RD || RL 
D
vo vsg
vi gmvsg
+

-
 Solution Small Signal Analysis : Voltage gain

1/gm
vsg

D
+
gmvsg

vi

1
vsg gm

vi 1   RD || RL 
gm
 Solution Small Signal Analysis : Voltage Gain

1/gm

D
+
gmvsg

vi

vi  vsig
Rin  
 Solution Small Signal Analysis : Voltage Gain
vo vo vsg vi 1
   vsg gm
vsig vsg vi vsig 
vi 1   RD || RL 
gm
vo
  g m  RD || RL 
vsg vi  vsig

 1
vo gm
  g m(RD||RL ) 
vsig 1  (RD || RL )
gm

vo (RD||RL )

vsig 1  (RD || RL )
gm
 Solution Small Signal Analysis : Voltage Gain

vo vo vi
1/gm
 
vsig vi vsig
-

D
vo

 RD || RL 
1   R || R 
+
gmvsg vi
vi
+ gm D L

-
vi  vsig

vo

 RD || RL 
vsig 1   RD || RL 
gm
 Solution Small Signal Analysis

Rin  (   1) re  RC || RL  Rin  

 Rsig    1
Rout  RC || re   Rout  RD ||
 (1   )   1 gm

vo (RC||RL ) Rin vo

 RD || RL 
  vsig 1   RD || RL 
vsig re  (RC || RL ) Rin  Rsig gm
Problem 6-127(e)
 DC Analysis 6-127(e)
  100
I E1  0.5mA
I B1  0.5 / 101  5A  0
I C1  0.5mA
  100
I E 2  0.5mA
I B 2  0.5 / 101  5A  0
I C 2  0.5mA
VC1  5  0.7  4.3V VC 2  10  0.5  10  5V
VC1  VB1  0.4V  10  5  (10) 3  0.4  0.4V VC 2  VB 2  0.4V  5  0.4V  4.6V
Q in Active mod e Q2 in Active mod e
1
Small Signal Model
Small Signal Model
 Small Signal Model

Rin

Rin  r 1
 Small Signal Model
+
+ vbe2

vbe1 -

Rout

vbe1  0
vbe 2  0
Rout  RC  Vsig  0
 Small Signal Model

vo vo veb 2 vbe1
  
vsig veb 2 vbe1 vsig
vo veb 2 vbe1 r 1
 g m 2 RC   g m1re 2 
veb 2 vbe1 vsig r 1  Rsig
vo  g m 2 RC g m1re 2 r 1  1 2 RC
 
vsig Rsig  r 1 Rsig  r 1
 Problem6-127(f)
Replacing BJT with MOSFET
Small Signal Model
Small Signal Model
 Small Signal Model

Rin

Rin   Rout

Rout  RD  Vsig  0
vo vo vsg 2 v gs1 vo vsg 2 g m1
    g m 2 RD  vsg1  vsig
vsig vsg 2 v gs1 vsig vsg 2 v gs1 gm2

vo  g m 2 RD g m1
   g m1 RD
vsig gm2
 Rin  r 1
Rin  
Rout  RC
vo  1 2 RC
   Rout  RD
vsig Rsig  r 1
 1 vo
vo   2 RC   g m1 RD
 vsig
vsig Rsig 1

1 g m1
Problem 6-127(f)
Solution P6-127(f)

+
vbe2

-
+

veb1

-
 Solution P6-127(f)
vb1
Rin   (1  1 )(re1  re 2 )
ib1
Rout  RL
+ vO vO vbe 2 vi
vbe2
  
+
- vsig vbe 2 vi vsig
veb1

+ vbe 2  re 2

vi vi re1  re 2
-
vi Rin (1  1 )(re1  re 2 )
 
vsig Rin  Rsig (1  1 )(re1  re 2 )  Rsig
Problem 6-127(f) with MOSFET
Solution P6-127(f)

vgs2

-
+

vsg1

-
 Solution P6-127(f) vi
Rin  
ig1
+

vgs2
vO vO v gs 2 vi
-   
+ vsig v gs 2 vi vsig
vsg1

-
ig1=0
+
vi

v gs 2  1
-
gm2  g m1
 
vi 1  1 g m1  g m 2
g m1 gm2
vi  vsig
 Comparison BJT/MOSFET Cct

Rin  (1  1 )(re1  re 2 )
Rin  
Rout  RL  
 1
vo (1  1 ) 2 RL

vsig (1  1 )(2re )  Rsig
 Problem 6-123
VBE=0.7 V

β =200

K’n(W/L)=2mA/V2

Vt=1V

Figure P6.123
DC Analysis

Figure P6.123
VBE=0.7 V

β =200
DC Analysis
K’n(W/L)=2mA/V2
I D1  I S1  o.1mA, I B2  0
Vt1=1V

1mA
W 
I D1 1  K 'n  VGS  Vt 
Vt2=25mV
2
2 L

0.1  1  2VGS  1  VGS  1.316V

2V
2
2
IG=0
0.7V

VC 2 V GSV BE 2V

52
I=0.7/6.8=0.1mA I  I C 2  1mA
3

2 I D1
g m1   0.63mA / V
VVOV

I C2 
g m2   40mA / V , r 2   5k
Vt gm2
Small Signal Model
Small Signal Model
 Small Signal Model : Voltage Gain
vo v v v
 o  be 2  i
vsig vbe 2 vi v gs1
vo
  g m 2 ( RL || RC )  -30V/V
vbe 2
Negelecting effect of RG  10M
ig=0
+
vbe 2 ( RS 1 ||r  2 )
  0.64V / V
vi 1
vi +
 ( RS 1 ||r  2 )
vbe2 g m1
- -
vi Rin
  0.83V / V
vsig Rin  Rsig
v0 ( RS1 ||r  2 ) Ri n
  g m 2 ( RL || RC )    16V / V
1
vsig  ( RS1 ||r  2 ) Rin  Rsi g
g m1
Small Signal Model : Input Resistance

ii

ig=0
+

vi

Rin v0 ( RS1 ||r  2 )

  g m 2 ( RL || RC )   19.2V / V
vi 1
 ( RS 1 ||r  2 )
g m1
 Small Signal Model : Output Resistance

IRG

Itest

ig=0
+
Vtest = vo

vi

Rout
Vtest
Rout 
I test
The Miller Theorem.
The Miller equivalent circuit.
Miller Theorem

Z Z
Z1  Z2 
1 K 1
1
K
V1 V1  KV1 1  K 
I1  I V  
Z1 Z1  Z 
V1 Z
 Z1 
I1 1 K
0  V2 0  KV1 V1  KV1
I2  I 
Z2 Z2 Z
V2 Z
Z2  
I2 1 1
K
 Miller theorem
• Miller theorem states that impedance Z
can be replaced by two impedances: Z1
connected between node 1 and ground
and Z2 connected between node 2 and
ground where
Z Z
Z1  & Z2 
1 K 1
1
K
V2
where k  gain function
V1
to obtain the equivalent circuit
 Miller theorem
• Miller equivalent circuit is valid only as
long as the rest of the circuit remains
unchanged

• Miller equivalent circuit cannot be used

directly to determine the output resistance
of an amplifier. It is due to the fact for
output impedance test source is required
and thus circuit has a major change.
Circuit for Example 6.7.
 Example

Z1  1M
Z 100k
Z1    9.9k
1  K 1  100
Z
Z2   0.99M
1
1
K
VO VO V1
 
Vsig V1 Vsig
Z1
 100   497 V / V
Z1  Rsig
K=-100 V/V, Z = 1 M Ω
 OBSERVATIONS
• The Miller replacement for a negative
feedback results in a smaller resistance
[by a factor of (1-K)] at the input.

• The multiplication of a feedback

impedance by a factor (1-k) is referred as
Miller Multiplication or Miller Effect
 Small Signal Model
CE with RE includng r0
 A CE amplifier with emitter degeneration : Input Resistance

2
3

5
A CE amplifier with emitter degeneration : Input Resistance
 A CE amplifier with emitter degeneration to determine Avo.

Open Circuit Voltage Gain

Figure 6.49
 A CE amplifier with emitter degeneration

to determine Output Resistance

7
5

2
 Active-loaded common-base amplifier

Figure 6.33
 Active-loaded common-base amplifier

to determine Input Resistance

4 5

3
6

Figure 6.33
 Active-loaded common-base amplifier

With output open-circuit

6

7
5

8
2

Figure 6.33
 A CB amplifier to determine Output Resistance

7
5

2
Quiz No 8

DE 28 EE
Quiz No 8

DE 28 EE