Subject : LOGIC CIRCUITS

1 and 2

 Compiled by : Prof. Danilo M. Miranda, E.C.E.

XDH,XSH, TUPTFA PRESIDENT
– Faculty, Electrical & Allied,
– B Eng Department
ANALOG
A quantity is represented by a voltage,
current, or meter movement that is
proportional to the value of that quantity.
Example:
automobile speedometer

 CONTINUOUS
Digital
 The quantities are represented not by
proportional quantities but by symbols
called digits.
Example:
digital watch
 Discrete (step by step)
Advantages of Digital Techniques
 1. Easier to design.
 2. Information storage is easy
 3.Accuracy & Precision are greater
 4. Operation can be Programmed
 5. Less affected by noise
 6. Can Fabricated on IC.
Limitations of Digital techniques


THE WORLD
IS MAINLY ANALOG
Representing Binary Quantities
 Logic 1: Logic 0:
Representing Binary Quantities
 Logic 1: Logic 0:
Representing Binary Quantities
 Logic 1: Logic 0:
Representing Binary Quantities
 Logic 1: Logic 0:
Representing Binary Quantities
 Logic 1: Logic 0:
DATA
REPRESENTATION
Standard Digital Codes
Computers process information in digital form. Characters are
assigned a 7 or 8 bit code to indicate its character. This 7 or 8 bit code
becomes a number (usually hexadecimal) that the computer can work
with. The characters stored in a computer include the following:

Lower case letters:

a-z
Upper case letters:
A-Z
Digits:
0-9
Punctuation Marks:
. , ; : ! ? etc...
Unit Symbols:
# $ % & * etc...
Control Codes:
EOF, etc..
There are 2 major
codes existing today:
ASCII (pronounced ah-
skee) and EBCDIC
(pronounced eb-ce-dic).
EBCDIC - Extended Binary Coded
Decimal Interchange Code
EBCDIC is used mainly by IBM
mainframes and compatibles. It is
not common in the PC LAN world
unless you are connecting to the
IBM mainframe world. In order to
connect, you would require either
an IBM 3270 terminal emulation
program or a device called a
gateway.
Table 1 shows the EBCDIC translation
table. Computers speak in the binary
code of 1s and 0s: they do not
recognize the letter "A." Instead, they
refer to the letter "A" as the binary
number 1100 0001. It is not easy for
humans to remember binary numbers
such as 1100 0001, but it is easier to
remember the hexadecimal number
C1. The hexadecimal number C1 is
equal to the binary number 1100 0001.
The hexadecimal number C1 is
equal to the decimal number 193.
Table 1 shows both the decimal
(dec) number and the
hexadecimal (hex) number for
the capital letter "A". Lower case
"a" is represented by the EBCDIC
decimal code 129 (or,
hexadecimal code 81).
Besides character codes like the previous letter
"A", the EBCDIC code also defines control
characters. These are characters that have
special meaning. For example, the control
character FF stands for Form Feed, and is used
by printers to either advance a page or to eject a
page. The decimal code for FF is 12 and the
hexadecimal code is C.
Both hexadecimal and decimal codes are
indicated, because in many instances, a program
or interface will report the EBCDIC code in one of
the formats. You may have to use Table 18-1 to
translate from the numerical code to the actual
character.
Dec Hex Name Dec Hex Name Dec Hex Name Dec Hex Name

128 80 160 A0 192 C0 { 224 E0 \

129 81 a 161 A1 ~ 193 C1 A 225 E1 NSP

130 82 b 162 A2 s 194 C2 B 226 E2 S

131 83 c 163 A3 t 195 C3 C 227 E3 T

132 84 d 164 A4 u 196 C4 D 228 E4 U

133 85 e 165 A5 v 197 C5 E 229 E5 V

134 86 f 166 A6 w 198 C6 F 230 E6 W

135 87 g 167 A7 x 199 C7 G 231 E7 X

136 88 h 168 A8 y 200 C8 H 232 E8 Y

137 89 i 169 A9 z 201 C9 I 233 E9 Z

138 8A 170 AA 202 CA SHY 234 EA

139 8B 171 AB 203 CB 235 EB

140 8C 172 AC 204 CC 236 EC

141 8D 173 AD 205 CD 237 ED

142 8E 174 AE 206 CE 238 EE

143 8F 175 AF 207 CF 239 EF

144 90 176 B0 208 D0 } 240 F0 0

145 91 j 177 B1 209 D1 J 241 F1 1

146 92 k 178 B2 210 D2 K 242 F2 2

147 93 l 179 B3 211 D3 L 243 F3 3

148 94 m 180 B4 212 D4 M 244 F4 4

149 95 n 181 B5 213 D5 N 245 F5 5

150 96 o 182 B6 214 D6 O 246 F6 6

151 97 p 183 B7 215 D7 P 247 F7 7

152 98 q 184 B8 216 D8 Q 248 F8 8

153 99 r 185 B9 217 D9 R 249 F9 9

154 9A 186 BA 218 DA 250 FA

155 9B 187 BB 219 DB 251 FB

156 9C 188 BC 220 DC 252 FC

157 9D 189 BD 221 DD 253 FD

158 9E 190 BE 222 DE 254 FE

159 9F 191 BF 223 DF 255 FF EO

ASCII - American Standard Code for
Information Interchange
ASCII is the most popular code and it is
used by the majority of the computing
world. ASCII itself is a 7 bit code that
allows only 128 characters (27). Most
applications follow IBM's Extended
ASCII code, which uses 8 bits and
allows an addition 128 graphic
characters for a total of 256 characters
(28). We will be concentrating on 7 bit
ASCII codes.
The 8421 Binary Decimal Code:
In this code structure, each of the decimal digits (0-9) is
represented by a four-bit binary code as illustrated in Table 2-8.
Recall that with 4 bits the number of unique representations is
24=16. Thus there are 6 invalid four-bit combinations for the BDC
code.
DecimalBCD
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
Invalid Combinations
1010
1011
1100
1101
1110
1111
Table 2.. BCD code
 
Gray Code
Overview
Most students are familiar with the binary number system. Here is a
table of values comparing decimal numbers 0 through 8 with their
binary equivalent:
000 0
001 1
010 2
011 3
100 4
101 5
110 6
111 7
Now presume these same three bits, representing eight values, are
used to encode a level from 0 to 7 using a mechanical sensor. To go
from a level of 3 (code 011) to a level of 4 (code 100) requires all
three bits change at the same time. This physically does not happen
in the real world where mechanical sensors are involved. For
example, if the bit on the left changes just before the other two, the
output of the circuit would appear to go from 011 to 111 and then to
100, corresponding to a level change of 3 to 7 and then to 4. Clearly
this is not what was meant to be encoded.
One way to get around this problem is to use a
Gray code for the sequence. In this code, only
one bit position changes as the level changes
by one step. Here is a three-bit Gray code
equivalent for the eight levels shown above:
000 0
001 1
011 2
010 3
110 4
111 5
101 6
100 7
To see how this works, imagine a Gray code is being
used to convert the angular position of a control or
sensor into digital form. A line of sensors along the
radius of the disk reads the code off the surface of the
disk. If the disk is half-way between two positions
each sensor might read its bit from both positions at
once but since only one bit differs between the two,
the value read is guaranteed to be one of the two valid
values rather than some third invalid combination. So
a Gray code wheel going from level 3 to level 4 in the
above example would be either 010 (representing
level 3) or 110 (representing level 4).
Here is a peek at a Gray scale encoded wheel with 28
levels. You should be able to spot the codes for 3 and
4 on the wheel to convince yourself that no glitches,
like temporarily appearing to have some other output,
are possible.
Note that the bit position of any bit in the code is not an
indication of the weight of the bit, as in the binary number
system. The code must be decoded by looking up the level
corresponding to the bits in the Gray code.
 
LOGIC CIRCUIT / LOGIC
GATE :
Any circuit that behaves
according to a set of logic rules.
 LOGIC GATES:
1. OR Gate

A
B A+B=out
A B Out
0 0 0
0 1 1
Truth Table:
1 0 1
1 1 1
2. AND Gate

A
B AB=out
A B Out
0 0 0
Truth Table: 0 1 0
1 0 0
1 1 1
2. NOT Gate or Inverter

A A
A Out
0 1
Truth Table: 1 0
UNIVERSAL GATES
2. NAND Gat
A
B AB=out
A B Out
0 0 1
Truth Table: 0 1 1
1 0 1
1 1 0
 UNIVERSAL GATES
2. NOR Gate

A
B A+B=out
A B Out
0 0 1
0 1 0
Truth Table:
1 0 0
1 1 0
BOOLEAN ALGEBRA
 Post. 2 (a)X+0 = X (b)X * 0 = 0
 Theorem 2 (a)X+1 = 1
(b)X * 1 = X
 Theorem 1 (a)X+X = X

(b)X * X = X
 Post. 5 (a)X+X = 1
(b)X * X = 0
Commulative: (a)X + Y = Y + X (b)XY = YX
Associative: (a) X + (Y+Z)=(X+Y)+Z
(b)X(YZ)=(XY)Z
Distributive: (a)X(Y+Z)=XY + XZ
(b)X+YZ=(X+Y)(X+Z)
De Morgan: (a)(X+Y)=X Y
(b)(XY)=X + Y
Absorption: (a)X + XY = X
(b)X(X+Y)=X
Involution: X=X
ANOTHER PRESENTATION:
__
X = X’
Example:
_
A*A = A’ *A = 0
EXAMPLES:
1. Simplify the expression :
y =AB’D + AB’D’
= AB’(D+D’) by Postulate 5 a
= AB’

2. Z = (A’+B) (A+B)
= A’A +A’B + BA +BB by dist. Property
= 0 +A’B + AB + B by Post. 5b : Th. 1b
= B (A’ +A) + B by factoring
= B + B by theorem 1a
Z= B
Sum – Of – Products Form:
(SOP)
- each of these SOP expressions
consists of two or more AND
terms (products) that are Ored
together.
Examples:
1. ABC + A’BC’
2. AB= A’BC’ + C’D’ +D
3. A’B +CD’+EF+GK+HL’
Product – Of – Sums Form(POS)
- it consists of two or more OR
terms (sums) that are ANDed
together.
Examples:
1. (A + B’ +C) ( A+C)
2.(A+B’)(C’+D)F
3.(A+C)(B+D’)(B’+C)(A+D’+E’)
3. Z = ( A + B’ +C )’
= A’ [ ( B’*C)’]
=A’ [ B’’+C’ ]
= A’ [ B + C’ ]
= A’B + A’C’
4. W= [(A+BC)(D+EF)]’
= (A+BC)’ + (D+EF)’
= A’ (BC)’ + D’ (EF)’
= A’ ( B’+C’) + D’(E’+F’)
=A’B’ +A’C’ +D’E’ +D’F’
Seat Work:

1. Out = ABCDE

2. OUT = ABCD
UNIVERSALITY OF NAND & NOR GATES
Karnaugh map

A Karnaugh map (K-map) is a pictorial method used to

minimize Boolean expressions without having to use
Boolean algebra theorems and equation manipulations.
A K-map can be thought of as a special version of a
truth table.
Using a K-map, expressions with two to four variables
are easily minimized. Expressions with five to six
variables are more difficult but achievable, and
expressions with seven or more variables are extremely
difficult (if not impossible) to minimize using a K-map.
Forming Minimum Sum-of-Products from K-Map

Step 1:
Choose an element of ON-set not already covered by an implicant

Step 2:
Find "maximal" groupings of 1's and X's adjacent to that element.
Remember to consider top/bottom row, left/right column,
adjacencies. (always a power of 2 number of elements).
Repeat Steps 1 and 2 to find all prime implicants

Step 3:
Revist the 1's elements in the K-map. If covered by single prime
implicant, it is essential, and participates in final cover. The 1's it
covers do not need to be revisited

Step 4:
If there remain 1's not covered by essential prime implicants, then
select the smallest number of prime implicants that cover the
remaining 1's
 
 Simplification of Boolean
Functions
A. The MAP METHOD
* 2 Variables : A, B

10 10
A’ B’ A B’

10 10
A’ B AB
Example a:
Example a:

OUT = A’B’ +A’B

= A’
Example B:

OUT = A’B’ + AB
3 VARIABLES:
3 VARIABLES:

OUT = A’BC’+ABC’+A’BC+ABC
=B
OUT = A’B’C’ + A’B’C + AB’C’ +AB’C
= B’
3 VARIABLES:
OUT = A’C’+A’B+AC+BC
WORDED PROBLEM:
1.) A 4-bit number is represented
as A3 A2 A1 A0, where A3 A2
A1 and A0 represent the
individual bits with A0 equal to
the LSB. Design a logic circuit
that will produce a HIGH output
whenever the binary number is
greater than 0010 and less than
1000.
Seat work :
Figure 2. Shows a diagram for an automobile
alarm circuit used to detect certain
understanding conditions. The three switches
are used to indicate the status of the door by
the driver’s seat, the ignition, and the
headlights, respectively. Design the logic
circuit with these three switches as inputs so
that will be activated whenever either of the
following conditions exists:
* The headlights are on while the ignition is
off.
* The door is open while the ignition is on.
LET D = DOOR
I = IGNITION
L = LIGHT
3 VARIABLES:
Experiment No. 1
Combinational Logic Circuit

General Objectives:
1. To be able to understand the
basic principles of Logic Circuit
and Switching theory and its
principles.
Worded Problem:

Figure A. shows four switches that are part of

the control circuitry in a copy machine. The switches
are at various points along the path of the copy paper
, as the paper passes through the machine . Each
switch is normally open, and as the paper passes
over a switch , the switch closes. It is impossible for
switches S1 and S4 to be close at the same time .
Design the logic circuit to produce a HIGH output
whenever two or more switches are closed at the
same time. Use K-mapping and take advantage of
the don’t care conditions.
DON’T CARE
CONDITION

“X”
- IT IS EITHER
LOGIC 1 OR
LOGIC 0
ENCODERS

It has a number of input lines,

only one of which is activated at
a given time.
 Multivibrators
Two-state devices called multivibrators
are used extensively in digital
electronics. The bistable multivibrators
are called flip-flops and are the basic
memory devices used in sequential
logic. Other two-state devices include
the astable multivibrator which serves
as an oscillator and the
monostable multivibrator ("one-shot"
multivibrator) which can serve as a
pulse source.
 Flip-Flops
"Flip-flop" is the common name given to two-state
devices which offer basic memory for sequential logic
operations. Flip-flops are heavily used for digital data
storage and transfer and are commonly used in banks
called "registers" for the storage of binary numerical
data.

                                                                    
Edge-Triggered Flip-flops
An edge-triggered flip-flop
changes states either at the
positive edge (rising edge) or
at the negative edge (falling
edge) of the clock pulse on the
control input.  The three basic
types are introduced here: S-
R, J-K and D.
The S-R, J-K and D inputs are called synchronous
inputs because data on these inputs are
transferred to the flip-flop's output only on the
triggering edge of the clock pulse.On the other
hand, the direct set (SET) and clear (CLR) inputs
are called asynchronous inputs, as they are inputs
that affect the state of the flip-flop independent of
the clock.  For the synchronous operations to
work properly, these asynchronous inputs must
both be kept LOW.
Edge-triggered S-R flip-flop
As S = 1, R = 0.  Flip-
flop SETS on the
rising clock edge.
Edge-triggered J-K flip-flop
Edge-triggered D flip-flop
Pulse-Triggered (Master-Slave) Flip-flops
 Data Lock-Out Flip-flops
The data lock-out flip-flop is similar to the pulse-triggered (master-
slave) flip-flop except it has a dynamic clock input.  The dynamic
clock disables (locks out) the data inputs after the rising edge of the
clock pulse.  Therefore, the inputs do not need to be held constant
while the clock pulse is HIGH.  

The master section of this flip-flop is like an edge-triggered device.

 The slave section becomes a pulse-triggered device to produce a
postponed output on the falling edge of the clock pulse.

The logic symbols of S-R, J-K and D data lock-out flip-flops are
shown below.  Notice they all have the dynamic input indicator as
well as the postponed output symbol.
Operating Characteristics
 Propagation Delay Time - is the interval of time
required after an input signal has been applied
for the resulting output change to occur.

 Set-Up Time - is the minimum interval required

for the logic levels to be maintained constantly
on the inputs (J and K, or S and R, or D) prior
to the triggering edge of the clock pulse in order
for the levels to be reliably clocked into the flip-
flop.
Pulse Widths - are the minimum pulse widths specified
by the manufacturer for the Clock, SET and CLEAR
inputs.
 Hold Time - is the minimum interval required for
the logic levels to remain on the inputs after the
triggering edge of the clock pulse in order for the
levels to be reliably clocked into the flip-flop.

 Maximum Clock Frequency - is the highest rate

that a flip-flop can be reliably triggered.

 Power Dissipation - is the total power consumption

of the device.
Applications
 Frequency Division
Parallel Data Storage
 Counting
Counters can be classified
into two broad categories
according to the way they are
clocked:
 Asynchronous (Ripple) Counters - the
first flip-flop is clocked by the external
clock pulse, and then each successive
flip-flop is clocked by the Q or Q' output
of the previous flip-flop.

 Synchronous Counters - all memory

elements are simultaneously triggered by
the same clock.
Asynchronous (Ripple) Counters
Three-bit asynchronous binary counter
Asynchronous Decade Counters
Asynchronous Up-Down Counters
Synchronous Counters
Synchronous Decade Counters
Synchronous Up-Down Counters
Applications
 Introduction

Shift registers are a type of sequential logic circuit,

mainly for storage of digital data.  They are a
group of flip-flops connected in a chain so that
the output from one flip-flop becomes the input
of the next flip-flop.  Most of the registers possess
no characteristic internal sequence of states.  All
the flip-flops are driven by a common clock, and
all are set or reset simultaneously.
Serial In - Serial OutShift Registers
Serial In - Parallel Out Shift Registers
Parallel In - Serial OutShift Registers
A four-bit parallel in - serial out shift register
is shown below.  The circuit
Parallel In - Parallel Out Shift Registers
Bidirectional Shift Registers
Shift Register Counters

 Ring Counters
Johnson Counters
Shift Register Counters
Johnson Counters
Sequential Logic Circuits

 Figure 1. Block Diagram of Sequential

Circuit.

Figure 1. Block Diagram of

Sequential Circuit.
Synchronous and Asynchronous Operation

Figure 2. Clock Signal

Summary of the Types of Flip-flop Behaviour
CHARACTERISTIC
TABLE EXCITATIO
N TABLE

S R Q(next) Q Q(next) S R
0 0 Q 0 0 0 X
0 1 0 0 1 1 0
1 0 1 1 0 0 1
1 1 ? 1 1 X 0

J K Q(next) Q Q(next) J K
0 0 Q 0 0 0 X
0 1 0 0 1 1 X
1 0 1 1 0 X 1
1 1 Q'
1 1 X 0
Continuation…
EXCITATION
TABLE
CHARACTE- Q
Q(next) D
RISTIC
TABLE
0
0 0
D Q(next) 0
1 1
0 0 1
0 0
1 1 1
1 1

T Q(next) Q
Q(next) T
0 Q 0
0 0
1 Q' 0
1 1
1
0 1
1
1 0
Analysis of
Sequential Circuits

Figure 6. Analysis procedure of

sequential circuits.
State Tables and State Diagrams

 We have examined a general model for sequential

circuits. In this model the effect of all previous
inputs on the outputs is represented by a state of the
circuit. Thus, the output of the circuit at any time
depends upon its current state and the input. These
also determine the next state of the circuit. The
relationship that exists among the inputs, outputs,
present states and next states can be specified by
either the state table or the state diagram.
State Table

 The state table representation of a sequential circuit

consists of three sections labelled present state, next
state and output. The present state designates the
state of flip-flops before the occurrence of a clock
pulse. The next state shows the states of flip-flops
after the clock pulse, and the output section lists the
value of the output variables during the present
state.
State Diagram

 In addition to graphical symbols, tables or

equations, flip-flops can also be represented
graphically by a state diagram. In this diagram, a
state is represented by a circle, and the transition
between states is indicated by directed lines (or
arcs) connecting the circles. An example of a state
diagram is shown in Figure 3
 Figure 3. State
Diagram
Example: This example is taken from P. K. Lala,
Practical Digital Logic Design and Testing, Prentice
Hall, 1996, p.155.
 Consider a sequential circuit
shown in Figure 4. It has one
input x, one output Z and
two state variables Q1Q2
(thus having four possible
present states 00, 01, 10, 11).

Figure 4. A Sequential Circuit

The behaviour of the circuit is determined by the following
Boolean expressions:
       Z = x*Q1
    D1 = x' + Q1
    D2 = x*Q2' + x'*Q1'
Present State Next State Output
Q1Q2 x=0 x=1 x=0 x=1

00 11 01 0 0
01 11 00 0 0
10 10 11 0 1
11 10 10 0 1
 Figure 5. State
Diagram of
circuit in Figure
4.
 NAME STATE DIAGRAM

SR

JK

State Diagrams of Various Flip-flops

Analysis of
Sequential
Circuits

Figure 6. Analysis procedure of

sequential circuits
Design of
Sequential
Circuits
Design of Sequential Circuits
This example is taken from M. M. Mano, Digital Design, Prentice Hall, 1984, p.235.

Example 1.3   We wish to design a synchronous sequential circuit

whose state diagram is shown in Figure 13. The type of flip-flop to be
use is J-K.

 Figure 13. State

diagram
 Table 9. State table.

Present State Next State

Q0 Q1 x=0 x=1

00 00 01
01 10 01
10 10 11
11 11 00

Table 10. Excitation table for JK flip-flop

Output Transitions Flip-flop inputs
Q Q(next) JK

0      0 0  X
0  1 1  X
1      0 X  1
1      1 X  0
 Flip-flop
Present State Next State Input Inputs
Q0 Q1 Q0 Q1 x J0K0 J1K1

00 00 0 0X 0X
00 01 1 0X 1X
01 10 0 1X X1
01 01 1 0X X0
10 10 0 X0 0X
10 11 1 X0 1X
11 11 0 X0 X0
11 00 1 X1 X1

Table 11. Excitation table of the circuit

Figure 14. Karnaugh Maps
The flip-flop input functions are derived:

J0 = Q1*x'        K0 = Q1*x
J1 = x                K1 = Q0'*x' + Q0*x = Q0¤x

Note: the symbol ¤ is exclusive-NOR.

 Figure 15. Logic diagram
of the sequential circuit
Design of Sequential Circuits
This example is taken from P. K. Lala, Practical Digital Logic Design and Testing, Prentice Hall, 1996, p.176 .

Example 1.4     Design a sequential circuit whose state tables are
specified in Table 12, using D flip-flops.

    Present       Next

State State         Output
Q0 Q1 x=0 x=1 x=0 x=1

00 00 01 0 0
01 00 10 0 0
10 11 10 0 0
11 00 01 0 1

Table 12. State table of a sequential circuit.

Table 13. Excitation table for a D flip-flop.

Output Transitions Flip-flop inputs

QQ(next) D

0      0 0
0  1 1
1      0 0
1      1 1
Table 14. Excitation table

Flip-
Present flop
State Next State Input Inputs Output
Q0 Q1 Q0 Q1 x D0 D1 Z

00 00 0 0 0 0
00 01 1 0 1 0
01 00 0 0 0 0
01 10 1 1 0 0
10 11 0 1 1 0
10 10 1 1 0 0
11 00 0 0 0 0
11 01 1 0 1 1
Figure 16. Karnaugh maps
The simplified Boolean expressions are:
      D0 = Q0*Q1' + Q0'*Q1*x
      D1 = Q0'*Q1'*x + Q0*Q1*x + Q0*Q1'*x'
        Z = Q0*Q1*x
Figure 17. Logic diagram of the sequential circuit.
(Solution at the Handouts)
 SeatofWork:
Design Counters
This example is taken from T. L. Floyd, Digital Fundamentals, Fourth Edition,
Macmillan Publishing, 1990, p.395.

 A counter is first described by a state

diagram, which is shows the sequence of
states through which the counter advances
when it is clocked. Figure 18 shows a state
diagram of a 3-bit binary counter. Use
Negative edge triggered JK FF’s and T FF’s.
(Solution at the Hand – Outs )
 Figure 18. State
diagram of a 3-
bit binary
counter.
ECE 3110: Introduction to Digital Systems

Chapter 6
Combinational Logic Design Practices

Adders, subtractors,
ALUs
Source:http://iweb.tntech.edu/oelkeelany/31
10S07/lectures/Lec5-10.ppt
 Prev…
 XOR (2-level, 3-level)
 Equivalent symbols
 XNOR
 Parity Circuits (Odd, even)
 Daisy chain
 Tree
 Comparators
 Iterative
 Parallel
Adders/Subtractors
 Half Adder
 Full Adder
 Ripple Adder

 Full Subtractor
 Ripple Subtractor
 Adder/ Subtractor Circuit
 Half Adder: adds two 1-bit
operands
 Truth table :

X Y HS=(X+Y) CO X
0 0 0 0 HS
Y
0 1 1 0
1 0 1 0 CO
1 1 0 1

HS  X  Y
CO  X  Y
 Full Adders: provide for carries
between bit positions
 Basic building block is “full adder”
 1-bit-wide adder, produces sum and carry outputs
 Truth table:
 Full Adders: provide for carries
between bit positions
 Basic building block is “full adder”
 1-bit-wide adder, produces sum and carry outputs
 Truth table:
X Y Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 Full Adders: provide for carries
between bit positions
 Basic building block is “full adder”
 1-bit-wide adder, produces sum and carry outputs
 Truth table:
X Y Cin S Cout
S is 1 if an odd number 0 0 0 0 0
of inputs are 1. 0 0 1 1 0
0 1 0 1 0
COUT is 1 if two or 0 1 1 0 1
more of the inputs are 1 0 0 1 0
1. 1 0 1 0 1
Recall: Table 2-3, pp32 1 1 0 0 1
1 1 1 1 1
Full-adder circuit
Full-adder circuit
Full-adder circuit
Ripple adder

 Speed limited by carry chain

 Faster adders eliminate or limit carry chain
 2-level AND-OR logic ==> 2n product terms
 3 or 4 levels of logic, carry look-ahead
 74x283
4-bit adder

 Uses carry
look-ahead
internally
16-bit group-
ripple adder
Subtraction
 Subtraction is the same as addition of the
two’s complement.
 The two’s complement is the bit-by-bit
complement plus 1.
 Therefore, X – Y = X + Y’ + 1
Full Subtractor = full adder, almost

 X,Y are n-bit unsigned binary numbers

 Addition : S=X+Y
 Subtraction : D = X - Y = X + (-Y) =
= X+ (Two’s Complement of Y)
= X+ (One’s Complement of Y) + 1
= X+ Y’+ 1
Full Subtractor = full adder, almost

 X,Y are n-bit unsigned binary numbers

 Addition : S=X+Y
 Subtraction : D = X - Y = X + (-Y) =
= X+ (Two’s Complement of Y)
= X+ (One’s Complement of Y) + 1
= X+ Y’+ 1
 Using Adder as a Subtractor

 Ripple Adder can be used as a Subtractor by inverting Y and setting the initial carry ( CIN ) to 1
 Using Adder as a Subtractor

 Ripple Adder can be used as a Subtractor by inverting Y and setting the initial carry ( CIN ) to 1
 MSI Arithmetic Logic Units (ALU )
74x181
 ALU performs Arithmetic and Logical Functions
S0
- A , B : 4 bits inputs
- S3,S2,S1,S0 : Function select S1
G
- M=0 : Arithmetic operations +=Plus , - = Minus S2
M=1 : Logical operations : += OR , . =AND S3 P

 Example : M A=B
Inputs Functions CIN
S3 S2 S1 S0 M=0 M=1 A0 F0
0 0 0 0 F= A-1+CIN F=A’ B0 F1
0 1 1 0 F= A-B-1+CIN F=A XOR B’ A1 F2
1 0 0 1 F= A+B+CIN F=A XOR B B1 F3
1 0 1 1 F=(A OR B)+ CIN F=A+B
A2
1 1 0 0 F= A+A+CIN F= 0000 COUT
B2
1 1 1 1 F=A+CIN F=A
A3
B3
Buffer or Driver
A Y
YA
Symbol Equation

Truth
Table
A Y

0 0

1 1
Tri-State Buffer or Driver
E

A Y
YA
Symbol Equation

Truth
Table
A E Y

0 0 Z
Z = high
0 1 0
impedance
1 0 Z

1 1 1
Memory Storage Registers

Latches and Flip-Flops

 D-Latch with (P)reset
Symbol
Pre d = “don’t care”
D E Pre Rst Qn+1
D SET Qn+1
D Q d d 1 0 0
E E
d d 0 1 1
Q
CLR d 0 1 1 Qn
Rst 0 1 1 1 0
1 1 1 1 1

Equation (level Truth

clock) Table Q → 1 immediate
Qn 1  EQn  EDnWhen Pre/SET (Preset) is asserted,
•
• When Rst/CLR (Reset) is asserted, Q → 0 immediate
• When neither SET nor CLR is asserted,
• Q → D (data) when E (enable) is asserted;
D Flip-Flop
Positive Edge Triggered
Symbol
Pre
D Clk Pre Rst Qn+1

D D
SET
Q
Qn+1 d d 1 0 0
Clk d d 0 1 1
CLR
Q d 0 1 1 Qn

Rst
d 1 1 1 Qn
0 1 1 0
1 1 1 1
Equation (rising
clock) Truth
Qn 1  Dn Table
• Q changes to D on rising edge of Clk
Basic Memory Devices
 Registers
 Basic

 Multi-Function (Shift, Load, Hold, . . .)

 Counters
 Asynchronous

 Synchronous

 Up / Down

 Modulo Counters
 MEMORY DEVICES
Source:http://notes.ump.edu.my/fkee/BEE1213/Addie/Chapt
er%209%20-%20%20Memory%20Devices.ppt
 MEMORY TERMINOLOGY
 Memory Cell – A device or an electrical circuit used to store a single
bit (0 or 1). Ex: flip-flop
 Memory Word – A group of bits (cells) I memory that represents
instructions or data of some type. Ex: Register consisting of 8 FFs
can be considered to be a memory
 Byte – A special term used for a group of 8 bits
 Capacity –A way of specifying how many bits can be stored in a
particular memory device or complete memory system. Ex : memory
that can store 4096 20-bit words. Total capacity of 81,920 bits.
(4096x20). The number of words in a memory is often a multiple of
1024. 1K represent 1024=210. 1M = 220=1,048,576.
1G=230=1,073,741,824
EXAMPLE
A certain semiconductor memory chip is specified as
2K x 8. How many words can be stored on this chip?
What is the word size? How many total bits can this
chip store?
Solution: 2K = 2 x 1024 = 2048 words
Each word is 8-bits (one byte). The total number of bits
is therefore
2048 x 8 =16,384 bits
EXAMPLE
Which memory stores the most bits: a 5M x 8 memory
or a memory that stores 1M words at a word size of 16
bits?
Solution:
5M x 8 = 5 x 1,048,576 x 8 = 41,943,040 bits
1M x 16 = 1,048,576 x 16 =16,777,216 bits
The 5M x 8 memory stores more bits.
MEMORY TERMINOLOGY
 Density- Another term for capacity
 Address – A number that identifies the location of a word
in memory.
 Read operation – the operation whereby the binary word
stored in a specific memory location (address) is sense and
then transferred to another device.
 Write operation – The operation whereby a new word is
placed into a particular memory location.
 Access Time – A measure of memory device’s operating
speed. It is the amount of time required to perform a read
operation.
MEMORY TERMINOLOGY
 Volatile Memory – Any type of memory that requires the
application of electrical power in order to store
information. If electrical power is removed, all information
stored in the memory will be lost
 Random-Access Memory (RAM) – Memory in which the
actual physical location of a memory word has no effect on
how long it takes to read from or write into that location
 Sequential-Access Memory (SAM)- A type of memory in
which the access time is not constant but varies depending
on the address location.

 MEMORY TERMINOLOGY
 Read/Write Memory – Any memory that can be read or written
into with equal ease
 Read-Only Memory (ROM). A broad class of semiconductor
memories designed for applications where the ratio of read
operations to write operations is very high.
 Static Memory Devices – Semiconductor memories devices in
which the stored data will remain permanently stored as long as
power is applied, without the need for periodically rewriting the
data into memory
 Dynamic Memory Devices – Semiconductor memory devices in
which the stored data will not permanently stored, even with power
applied, unless the data are periodically rewritten into memory.
MEMORY TERMINOLOGY
 Main Memory – Also referred to as the computer’s
working memory. It stores instructions and data the CPU is
currently working on. It is the highest-speed memory in
the computer and is always a semiconductor memory.
 Auxiliary Memory – Also referred to as mass storage
because it stores massive amounts of information external
to the main memory. It is slower in speed than main
memory and is always nonvolatile. CDs are common
auxiliary devices.
READ-ONLY MEMORIES
 The read-only memory is type of semiconductor memory
designed to hold data that either are permanent or will not
change frequently.
 During normal operation data can be read from ROM.
 Data can be entered electrically –programming or burning-
in the ROM.
 Some ROMs cannot have their data changed once they have
been programmed; others can be erased and reprogrammed
as often as desired.
 A major use for ROMs is in the storage of programs in
microcomputers. When the microcomputer is turned on, it
can immediately begin executing the program stored in
ROM
ROM BLOCK DIAGRAM
 ROM BLOCK DIAGRAM
 Has 3 sets of signals: address inputs, control inputs, and data
outputs.
 Store 16 words because it has 24=16 possible addresses, and each
word contains 8-bit because there are 8 data outputs.
 This is a 16 x 8 ROM.
 The most common numbers of data outputs for ROMs are 4, 8,16
bits with 8-bit word being the most common.
 Control input CS-Chip Select – an enable input that enables or
disabled the ROM outputs
 Many ROMs have two or more control inputs that must be active
in order to enable the data outputs so that data can be read from
the selected address.
ROM BLOCK DIAGRAM
 CS input shown in figure is active-LOW; therefore, it must
be in the LOW state to enable the ROM data to appear at
the data outputs
 Notice that there are no R/W input because the ROM
cannot be written into during normal operation.
 THE READ OPERATION
 16 different data words are stored at the 16 different address
locations.
 In order to read a data word from ROM, we need to do 2
things :
 Apply the appropriate address inputs
 Activate the control inputs.
 Ex: if we want to read the data stored at location 0111 of the ROM, we
must apply A3A2A1A0=0111 to the address inputs and then apply a
LOW to CS. The address inputs will be decoded inside the ROM to
select the correct data word, 11101101, that will appear at outputs D7
to D0. If CS is kept HIGH the ROM outputs will be disabled and will
be in the Hi-Z state.
TYPES OF ROM
MASK PROGGRAMMED ROM
 Has its storage location written into by the manufacturer
according to the customer’s specifications.
 A mask is used to control the electrical interconnections on the
chip.
 A special mask is required for each different set of information
to be stored in the ROM.
 Disadvantage – of this type of ROM is that cannot be
reprogrammed in the event of a design change requiring a
modification of the stored data
 Is the most economical approach when a large quantity of
identically programmed ROMs are needed.
TYPES OF ROM
PROGRAMMABLE ROM
(PROM)
 For lower-volume applications, manfacturers have
developed fusible-link PROMs that are user-
programmable; that is, they are not programmed
during the manufacturing process but are custom-
programmed by the user.
 Once programmed, cannot be erased and
reprogrammed
 If the programmed in the PROM must be changed,
the PROM must be thrown away.
 ERASABLE
PROGRAMMABLE ROM
(EPROM)
 Can be programmed by the user and can be erased
and reprogrammed as often as desired.
 Nonvolatile memory that will hold its stored data
indefinitely
 The programming process is usually performed by
a special programming circuit that is separate from
he circuit in which the EPROM will eventually be
working.
 EPROMs are available in a wide range of capacities
and access times; devices with a capacity of 512K x
8 and can access time of 20 ns are commonplace
ERASABLE
PROGRAMMABLE ROM
(EPROM)
Disadvantages:
1. They must be removed from their circuit to be erased
and reprogrammed
2. The erase operation erases the entire chip-there is no
way to select only certain addresses to be erased
3. The erase and reprogramming process can typically take
20 minutes or more.
ERASABLE
PROGRAMMABLE ROM
(EPROM)
ELECTRICALLY ERASABLE
PROM (EEPROM)
 The disadvantages of the EPROM were overcome by the
development of the electrically erasable PROM (EEPROM) as
an improvement over the EPROM.
 The erasing and programming of an EPROM can be done in
circuit ( without UV light source and a special PROM
programmer unit)
 Advantages: ability to erase and rewrite individual bytes (8-bit
words) in the memory array electrically.
 During a write operation, internal circuitry automatically erases
all of the cells at an address location prior to writing in the new
data. This byte erasability makes it much easier to make
changes in the data stored in an EEPROM
 CD ROM
 The disks are manufactured with a highly reflective surface.
 To store data on the disks, a very intense laser beam is focused on a very
small point on the disks. The heat from this beam burns a light diffracting
pit at that point on the disk surface.
 Digital data are stored on the disk one bit at a time by burning or not
burning a pit into the reflecting coating
 The digital information is arranged on the disk as a continuous spiral of
data points
 In order to read the data, a much less powerful laser beam is focus onto the
surface of the disk.
 At any point the reflected light is sensed as either a 1 or a 0.
 This optical system is mounted on a mechanical carriage that moves back
and forth along the radius of the disk, following the spiral of data as the
disk rotates.
FLASH MEMORY
 Flash memory cell is like the simple singe-transistor EPROM
cell, being only slightly larger.
 Allows electrical erasability but can be built with much higher
densities than EEPROMs.
 The cost of flash memory is considerably less than for
EEPROM
 Rapid erase and write times.
 Use bulk erase operation in which all cells on the chip are erase
simultaneously
 This bulk erase process typically requires hundreds of
milliseconds compares to 20 minutes for UV EPROMs
 RAM
 Any memory address location is as easily accessible as
any other.
 Is used in computers for the temporary storage of
programs and data.
 The contents of many RAM address locations will be read
from and written to as the computer executes a program.
This requires fast read and write cycle times for the RAM
so as not to slow down the computer operation
 Disadvantage – it is volatile and will lose all stored
information if power is interrupted or turned off.
 Advantage- can be written into and read from rapidly
with equal ease
STATIC RAM (SRAM)
 Can store data as long as power is applied to the
chip.
 SRAM memory cells are essentially flip-flops that
will stay in a given state (store a bit) indefinitely
provide that power to the circuit is not interrupted.
 Main applications of SRAM are in areas where only
small amounts of memory are needed or where high
speed is required.
 DYNAMIC RAM (DRAM)
 High capacity, low power requirement, moderate
operating speed.
 DRAM stores 1s and 0s as charges on a small MOS
capacitor. Because of the tendency for these charges to
leak off after a period of time, DRAM require periodic
recharging or the memory cells; this called refreshing
the DRAM.
 Have 4 times the density of SRAM
 The main internal memory of the most personal
microcomputers uses a DRAM because of its high
capacity and low power consumption
Analog to Digital Conversion
Source:http://cslab.cnu.ac.kr/lecture/pro01/(5)ADC.ppt

255
Why ADC ?
 Digital Signal Processing is more popular
 Easy to implement, modify, …

 Low cost

 Data from real world are typically Analog

 Needs conversion system
 from raw measurements to digital data

 Consists of

 Amplifier, Filters

 Sample and Hold Circuit, Multiplexer

 ADC

Chap 0 256
  n bits ADC
 Number of discrete output

ADC Essentials level : 2n

 Quantum

 LSB size
 Basic I/O Relationship  Q = LSB = FS / 2n
 ADC is Rationing  Quantization Error
System  1/2 LSB

 x = Analog input /  Reduced by increasing n

Reference
• Fraction: 0 ~ 1

Chap 0 257
Converter Errors
 Offset Error
 Integral Linearity Error

 Differential Linearity Error

 Gain Error

 Nonlinear Error
 Can be eliminated by initial adjustments  Hard to remove

Chap 0 258
Terminologies
 Converter Resolution  Conversion Time
 The smallest change  Required time (tc) before the

required in the analog input converter can provide valid

of an ADC to change its output data
output code by one level  Converter Throughput Rate
 Converter Accuracy  The number of times the

 The difference between the input signal can be sampled

actual input voltage and the maintaining full accuracy
full-scale weighted  Inverse of the total time

equivalent of the binary required for one successful

output code conversion
 Maximum sum of all  Inverse of Conversion time if

converter errors including No S/H(Sample and Hold)

quantization error circuit is used

Chap 0 259
 More on Conversion Time
 Example
 8-bit ADC

 Conversion Time: 100sec

 Input voltage change during the  Sinusoidal input

conversion process introduces 

an undesirable uncertainty  Rate A sin(2

vi of change ft )
 Full conversion accuracy is dvi
realized only if this uncertainty   fA cos(2 ft )  2 fA
Let FS=22A
dt
is kept low below the
converter’s resolution
2A
2 fA 
 Rate of Change x tc  2 n tc
resolution 1
 LimitedftoLow  12.4of
frequency Hz12.4 Hz
 dV FS  2  tc
n
Few Applications
( ) max  n
dt 2 tc

Chap 0 260
S/H increase Performance
 S/H (Sample and Hold)
 Analog circuits that quickly

samples the input signal on  Example

command and then holds it
relatively constant while the  20 nsec aperture time
ADC performs conversion 1
 f   62.17 KHz
 Aperture time (ta) 2  ta
n

 Time delay occurs in S/H

circuits between the time

 Reasonably good for
the hold command is 100sec converter
received and the instant
the actual transition to the
hold mode takes place
 Typically, few nsec

Chap 0 261
Analog Input Signal
 Typically, Differential or Single-  Matching input signal and
ended input signal of a single
polarity input range
 Typical Input Range  Prescaling input signal
 0 ~ 10V and 0 ~ 5V using OP Amp
 If Actual input signal does not
 In a final stage of
span Full Input range
preconditioning circuit
 Some of the converter output

code never used

 By proportionally scaling
 Waste of converter dynamic down the reference signal
range  If reference signal is
 Greater relative effects of the
adjustable
converter errors on output

Chap 0 262
Converting bipolar to unipolar
 Input signal is scaled and an offset
is added
 Using unipolar converter when input Add
signal is bipolar offset
 Scaling down the input scaled
 Adding an offset

 Bipolar Converter
 If polarity information in output

is desired
 Bipolar input range

 Typically, 0 ~ 5V

 Bipolar Output

 2’s Complement

 Offset Binary

 Sign Magnitude

 …

Chap 0 263
Outputs and Analog Reference
Signal
I/O of typical ADC

 Errors in reference signal

 From
 Initial Adjustment
 Drift with time and
temperature
 Cause
 ADC output  Gain error in Transfer
 Number of bits characteristics
 8 and 12 bits are typical
 To realize full accuracy of ADC
 10, 14, 16 bits also available  Precise and stable
 Typically natural binary
 BCD (3½ BCD)
reference is crucial
• For digital panel meter, and digital  Typically, precision IC voltage
multimeter reference is used
• 5ppm/C ~ 100ppm/C

Chap 0 264
 Control Signals  HBE / LBE
 Start  From CPU
 From CPU  To read Output word after
 Initiate the conversion EOC
process  HBE
• High Byte Enable
 BUSY / EOC
 LBE
 To CPU • Low Byte Enable
 Conversion is in progress
 0=Busy: In progress
 1=EOC: End of
Conversion

Chap 0 265
A/D Conversion Techniques
 Counter or Tracking ADC
 Successive Approximation ADC
 Most Commonly Used

 Dual Slop Integrating ADC

 Voltage to Frequency ADC
 Parallel or Flash ADC
 Fast Conversion

 Software Implementation
 Shaft Encoder

Chap 0 266
Counter
Block diagram Type ADC
 Operation
 Reset and Start Counter

 DAC convert Digital output of

Counter to Analog signal

 Compare Analog input and

Output of DAC
 Vi < VDAC
• Continue counting
 Vi = VDAC
• Stop counting
 Digital Output = Output of
Counter
 Waveform  Disadvantage
 Conversion time is varied

 2n Clock Period for Full Scale

input

Chap 0 267
Tracking Type ADC
 Tracking or Servo Type  Can be used as S/H circuit
 By stopping desired instant
 Using Up/Down Counter
 Digital Output
to track input signal
continuously  Long Hold Time

 For slow varying input  Disabling UP (Down) control,

Converter generate
 Minimum (Maximum)

value reached by input

signal over a given period

Chap 0 268
Successive Approximation ADC
 Most Commonly used in  Block Diagram
medium to high speed
Converters
 Based on approximating the
input signal with binary code
and then successively revising
this approximation until best
approximation is achieved
 SAR(Successive
Approximation Register) holds
the current binary value

Chap 0 269
Successive Approximation ADC
 Circuit waveform  Conversion Time
 n clock for n-bit ADC
 Fixed conversion time
 Serial Output is easily
generated
 Bit decision are made in
serial order
 Logic Flow

Chap 0 270
 Dual Slope Integrating ADC
 Operation  Excellent Noise Rejection
T1
 Integrate  vi dt  High frequency noise cancelled
0
t2 out by integration
 Reset and integrate
0 Vr dt  Proper T eliminates line noise
1 i ( AVG )  t 2Vr
 Thus T v 1

t  Easy to obtain good resolution

 
vi ( AVG )  Vr 2
T1  Low Speed
 Applications
 If T = 60Hz, converter
 DPM(Digital Panel Meter), 1

DMM(Digital Multimeter), … throughput rate < 30 samples/s

Chap 0 271
Voltage to Frequency ADC
 VFC (Voltage to Frequency
Converter)
 Convert analog input
voltage to train of pulses
 Counter
 Generates Digital output by
counting pulses over a fixed
interval of time
Chap 0
 Low Speed
 Good Noise Immunity
 High resolution
 For slow varying signal
 With long conversion
time
 Applicable to remote data
sensing in noisy environments
 Digital transmission over
a long distance
272
Parallel or Flash ADC
 Very High speed conversion
 Up to 100MHz for 8 bit

resolution
 Video, Radar, Digital

Oscilloscope
 Single Step Conversion
 2n –1 comparator

 Precision Resistive Network

 Encoder

 Resolution is limited
 Large number of

comparator in IC

Chap 0 273
Software Implementation
 Implementation with  Limited Practical Use
software using  Availability of Good
microprocessor performance with very
 Counting reasonable Cost
 Shifting
 Inverting
 Code Conversion
 …

Chap 0 274
 Shaft Encoder  Binary Encoder
 Misalignment of mechanism

causes large error

 Elctromechanical ADC  Ex: 011  111 (180deg)
 Convert shaft angle to digital

output
 Encoding
 Optical or Magnetic Sensor

 Applications
 Machine tools, Industrial
 Gray Encoder
robotics, Numerical control
 Misalignment causes 1 LSB

error

Chap 0 275
ASM
Asynchronous
State Machine
End of presentations!

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