Unit IV: GATE LEVEL DESIGN

YOGESWARI TOLIA
KIT
DEPTT. OF ELECTRONICS

VLSI DESIGN
 GATE LEVEL DESIGN
• Basic Circuit Concepts ,
• Sheet Resistance RS And Its
Concept To MOS.
• Area Capacitance Units ,
• Delays,
.

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1 , VLSI DESIGN
ay
M
 Introduction
• The properties of IC interconnections and the
substrate are increasingly important factors
affecting the performance and operation of an
IC. They must be considered in the IC de-sign
loop. A failure to do so may result in lower than
expected performance, higher than expected
dissipation and/or unreliable or in-correct circuit
behavior.

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 Introduction
• Wiring-Up of chip devices takes place through various
conductive layers produced during the MOS processing and it
is therefore necessary to be aware of the resistive and
capacitive characteristics of each layers.
• Today, interconnects constitute the main source of delay in
MOS circuits
• We will examine:
– Sheet Resistance – Resistance / Unit Area
– Area Capacitance
Concept such as sheet resistance RS and standard unit capacitance
Cg, help in evaluating the effect of wiring and output capacitance.

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 The Wire

transmitters receivers

schematics physical

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 Interconnect Impact on Chip

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 Wire Models

Capacitance-only
All-inclusive model

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 Impact of Interconnect Parasitics
• Interconnect parasitics
– Reduce reliability
– Affect performance and power consumption
• Classes of parasitics
– Resistive
– Capacitive
– Inductive

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 Transistor source/drain parasitics
• Source/drain have significant capacitance,
resistance.
• Measured same way as for wires.

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 Sheet Resistance

• Sheet resistance is resistance of layer per

square area.
• Rs=Resistance of layer/square area
• Rs is completely independent of the area of
the square. It is depends on the thickness of
the MOS layers.

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 Sheet Resistance
• RAB = ρ L /A
• A= t x W A
• => RAB = ρ L/(t x W)
• Let L = W (square slab)
t w L
• RAB = ρ / t
• => RAB = ρ/t = Rs ohm / square

• R=Rs x L/W
B
RAB = ZRsh

Z = L/W
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 Depending on the various IC technologies the
sheet resistance of various layers are tabled :
LAYERS 5µm 2µm 1.2µm

METAL 0.03 0.04 0.04

DIFFUSION 10-150 20-45 20-45

POLYSI 15-100 15-30 15-30

NMOS 10K 20K 45K

CHANNEL
PMOS 25K 45K 45K
CHANNEL
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 PROBLEM
2ʎ
Find the resistance of
Nmos Channel of 5 µm technologies?

2ʎ

R=Rs x L/W
Rs for Nmos channel is 10k
2ʎ=5µm
R= 10 K x 5µm/5µm
=10KὨ

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 Resistor
• Resistors are made by doped silicon or
polysilicon on an IC chip
• Resistance is determined by Length, line
Width, Height, and Dopant concentration

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 Dealing with Resistance
• Selective Technology Scaling
• Use Better Interconnect Materials
– reduce average wire-length
– e.g. copper, silicides
• More Interconnect Layers
– reduce average wire-length
A silicide is a compound that has silicon with more electropositive
elements.
Examples: nickel silicide, NiSi :sodium silicide, Na2Si ; magnesium
silicide, Mg2Si Platinum silicide, PtSi ;Titanium silicide, TiSi2
;Tungsten silicide, WSi2
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 Modern Interconnect

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 Capacitance

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 Capacitors
• Charge storage device
• Memory Devices, esp. DRAM
• Challenge: reduce capacitor size while
keeping the capacitance
• High- dielectric materials

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 Capacitors
Dielectric Layer
Dielectric Poly 2
Layer
Poly
Si Si
Poly Si
Oxide
Si Poly 1
Heavily
Doped Si

Parallel plate Stacked Deep Trench

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 Capacitance
• Area capacitance of layers:

Forms the
capacitance Insulating medium

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 Area Capacitance of Layers
• Conducting layers are separated from each
other by insulators (typically SiO2)
• This may constitute a parallel plate capacitor,
C = є0єox A / D (farads)
• D = thickness of oxide, A = area,
• єox = 4 F/µm2 (SiO2)
• Area capacitance given in pF/µm2

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 AREA CAPACITANCE OF LAYER
• Capacitance is given by:

C A / D
C  A / D
C   0INSA / D
  / D  K  10  4
0 INS

C  K  10  4  A

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 Standard capacitance
• Standard capacitance is denoted by
Cg=ἐ0ἐins A/D
For 5µm Technologies
ἐ0ἐins/D=4X10E-4pF/µm2

A=WXL
W=2ʎ ; L=2ʎ

2ʎ=5 µm2
Cg=4X10E-4pF/µm2 X25µm2 =10E-2pF
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 Permittivity

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Capacitance Value in pF×10-4 /µm2
(5μm Technology)
Gate to Channel 4
Diffusion(Active) 1
Poly silicon to Substrate 0.4
Metal1 to substrate 0.3
Metal2 to substrate 0.2

Metal2 to metal 1 0.4

Metal2
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to polysilicon 0.3
VLSI Design
 Capacitance
• Standard unit for a technology node is the
gate - channel capacitance of the minimum
sized transistor (2λ x 2λ), having W=L=feature
Size ,given as Cg
• This is a ‘technology specific’ value

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Cg may be evaluated for any MOS process. For example ,for
5μm MOS Circuits

Area/Standard square= 5μm × 5μm =25 μm2(=area of minimum size transistor)

Capacitance value (From table)=4 ×10-4 pF/µm2

Thus Standard value Cg = 25 μm2 × 4 ×10-4 pF/µm2= 0.01 pF

1.Calculate the gate capacitance value of 5μm technology

minimum sized transistor with gate to channel capacitance
value is 8 ×10-4 pF/µm2
2.Calculate the gate capacitance value of 2μm technology
minimum sized transistor with gate to channel capacitance
value is 8 ×10-4 pF/µm2

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 DELAY
DELAY: Time taken for output to reach
63%of the value from initial value is
given by:
τ = Rs x Cg
Delay depends on the IC technologies in use,
For 5 µm technologies τ = 0.1ns
For 2 µm technologies τ = 0.64ns
For 1.2 µm technologies τ = 0.64 ns
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 Delay Unit

• For a feature size square gate, τ = Rs x Cg

One standard (feature size square) gate area capacitance being
charged through one feature size square of n-channel resistance
(that is,through Rs for an nMOS pass transistor channel ) as in the
figure
Time constant τ=(1 Rs (n channel) × 1Cg ) seconds

• i.e for 5µm technology, τ = 104 ohm/sq x 0.01pF = 0.1ns

• Because of effects of parasitics which we have not considered
in our model, delay is typically of the order of 0.2 - 0.3 ns
• Note that τ is very similar to channel transit time τsd

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 New Interconnect Materials

• Aluminium  Copper
– Lower resistivity
– Higher immunity to Electromigration

• SiO2  Low-k dielectrics

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 What causes delay?
• In MOS circuits Ideal MOS

capacitive loading is the VIN

VGS
I (VGS-VT)2 C

main cause
• Due to: VIN
– Device capacitance Vdd

– Interconnect
0
capacitance t

VOUT
delay
50% level
V C L Vdd
t  C   
I 2    Cox  Vdd W
0
t

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 MOSFET capacitances
• MOS capacitances have three origins:
– The basic MOS structure
– The channel charge
– The pn-junctions depletion regions
Gate
Source Drain
CGS CGB CGD

CSB CDB
Bulk

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Home Assignment:
1. Read and make your own notes ON
the following topics from Basic VlSI
Design by:Douglas A. Puknell
&K.Eshraghian:
Topic Page no.
Driving large capacitive load 99-102
Wiring capacitance 107-108
Choice of layers 109-110

May 1, 2020 VLSI Design