PENTIUM MICROPROCESSOR

PENTIUM PROCESSOR
● The Pentium is a widely-used personal computer
microprocessor from the Intel Corporation. First offered in
1993, the Pentium quickly replaced Intel’s 486
microprocessor as the microchip-of-choice in
manufacturing a personal computer. The original Pentium
model includes two processors on one chip that contains
3.1 million transistors.
● Clock frequency ranging from 60 to 66 MHz
FEATURES OF PENTIUM PROCESSOR

The primary changes in Pentium Processor were:

✓ Superscalar Architecture
✓ Dynamic Branch Prediction
✓ Pipeline Floating-Point Unit
✓ Separate 8K Code and Data Caches
✓ Writeback MESI Protocol in the Data Cache
✓ 64-Bit Data Bus
✓ Bus Cycle Pipelining
Pentium Architecture: Block Diagram
PENTIUM REGISTER
• Four 32-bit register (EAX, EBX, ECX, EDX)
• Four 16-bit register ( AX, BX, CX, DX)
• Eight 8-bit register ( AH, AL, BH, BL, CH, CL, DH, DL)
• Some registers have some special use
• ECX for count in loop instructions
PENTIUM REGISTER (Eflags)

• Flags never change for any data transfer or program control

operation.
• Some of the flags are also use to control features found in the
microprocessor
• C (carry) holds the carry after addition or borrow after
subtraction. Also indicates error conditions.

• P (parity) is the count of ones in a number expressed as

even or odd. Logic 0 for odd parity; logic 1 for even parity.If a number
contains three binary one bits, it has odd parity; if a number contains no
one bit , it has even parity

• A (auxiliary carry) holds the carry (half carry) after addition

or the borrow after subtraction between bit positions 3 and
4 of the result.
● Z (zero) shows that the result of an arithmetic or logic operation is
zero

● S (sign) flag holds the arithmetic sign of the result after an arithmetic
or logic executes.

● T (trap) the trap flag enables trapping through an on-chip debugging

feature.

● I (interrupt) controls the operation of the INTR ( interrupt request)

input pin.
● D (direction) selects increment or decrement mode for the DI and/or SI
registers.

● O (overflow) occurs when signed numbers are added or subtracted.

An overflow indicates the result has exedeed the capacity of the
machine

● IOPL used in protected mode operation to select the privilege level for
I/O devices

● TN (nested task) flag indicates the current tasked is nested within

another task in protected mode operation.
● RF (resume) used with debugging to control resumption of execution
after the next instruction.

● VM (virtual mode) flag bits selects virtual mode operation in a

protected mode system.

● AC (alignment check) flag activates if a word or a doubleword is

addressed on a non-word or non-doubleword boundary.

● VIF is a copy of the interrupt flag bit available to the pentium 4-

(virtual
interrupt)
● VIP (virtual) provides information about a virtual mode interrupt for
(interrupt pending) Pentium. Used in multitasking environments to
provide virtual interrupt flags.

● ID (identification) flag indicates that the Pentium microprocessor

support the CPUID instruction. CPUID instruction provides the system
with information about the Pentium microprocessor.
CONTROL REGISTER
● CD cache disable controls the internal cache. If CD = 1, the cache will not fill
with new data . If CD = 0 misses will cause the cache to fill new data.

● NW not write through selects the mode of operation for the data cache. Iof
NW = 1, the data cache is inhibited from cache write through

● AM alignment mask enables alignment checking when set , it only occurs for
protected mode.

● WP write protect protects users level pages against supervisor level write
operations. When WP = 1, the supervisor can write to user level segment.

● NE numeric error enables standard numeric coprocessor error detection.

PIN DIAGRAM
CLOCK
● CLK- Clock (input)
○ Fundamental timing for the Pentium.

○ The CPU uses this signal as the internal processor clock.

● BF – Bus Frequency (input)
○ Bus Frequency determines the bus-to-core frequency ratio.

○ When BF is strapped to Vcc, the processor will operate at a 2 to 3 bus to

core frequency ratio.

○ When BF is strapped to Vss, the processor will operate at a 1 to 2 bus to

core frequency ratio.
INITIALIZATION

● RESET- (input)
○ Force the CPU to begin execution at a known state.
● INIT – initialization (input)
○ The Pentium processor initialization input pin forces the Pentium
processor to begin execution in a known state.

○ The processor state after INIT is the same as the state after
RESET except that the internal caches, write buffers, and floating
point registers retain the values they had prior to INIT.
ADDRESS BUS
● A31;A3- ADDRESS bus lines
○ OUTPUT except for cache snooping

○ The number of the address lines determines the amount of memory

supported by the processor.

○ Determines where in the 4GB memory space or 64K10 space the

processor is accessing.

○ These are input lines when AHOLD & EADS# are active for Inquire Cycle
(snooping)
ADDRESS BUS
● BE7#:BEO#: Byte Enable lines (Outputs)
● Bytes Enables to enable each of the 8 bytes in the 64-bit data
path.
○ Helps define the physical area of memory or I/O accessed.

○ The Pentium uses Byte Enables to address locations within a QWORD.

○ In effect a decode of the address lines A2-A0 which the Pentium does not
generate.

○ Which lines go active depends on the address, and whether a byte, word,
double word or quad word is required.
ADDRESS MASK

● A20M#: Address 20 Mask (input)

○ Emulates the address wraparound at a 1 Mbyte which occurs on
the 8086.

○ When A20M# is asserted , the Pentium processor masks physical

address bit 20 (A20) before performing a lookup to the internal
caches or driving a memory cycle on a bus.

○ A20#M must be asserted only when the processor is in real mode

Internal Parity

● IERR# - Internal Error (output)

○ Alerts System of Internal Parity Errors
Address Parity
● AP Address Parity (I/O)
○ Bi-directional address parity pin for the address lines.

○ Address parity is given by the Pentium processor with even parity

information on all CPU generated cycles in the same clock that
the address is driven.

○ Even parity must be driven back to the CPU during inquire cycles
on this pin in the same clock as EADS#.

○ Not supported on all systems.

Address Parity

● APCHK#: Address Parity Check Signal (output)

○ The status of the address parity check is driven on the APCHK#
output

○ Even Parity Checking

Data Bus
● D63:D)-Data Lines(I/O)

○ The bi-directional 64-bit data path to or from the CPU

○ The signal W/R# distinguishes direction.

○ during reads ,the CPU samples the data bus when BRDY# is asserted.
● DP7:DP0 – Data Parity (I/O)

○ Bi-directional data parity pins for the data bus.

○ Even Parity Check. One for each byte of the data bus

○ Output on writes, input on reads

○ Not supported on all systems

Bus Control
● ADS# - Address Strobe (output)
○ Indicates that a new valid bus cycle is currently being driven by the Pentium
processor

○ The following are some of the signals which are valid when ADS# = 0

■ Address (A31:3);Byte Enables (BE7#:0#);Bus cycle definition (M/IO# ; D/C#;

W/R#, CACHE#)

○ From power-on the ADS# signal should be asserted periodically when bus cycles
are running
Bus Control
● BRDY# - Burst Ready (input)

○ Transfer complete indication.

○ The bus ready input indicates that the external system has presented data on the data pins in
response to a read or that the external system has accepted the Pentium processor data in
response to a write request.

○ This signal ends the current bus cycle and is used to extend bus cycles to allow slow device
extra time.

○ If LOW (non-burst cycles), this signal ends the current bus cycle and the next bus cycle can
begin

○ If HIGH the pentium is prevented from continuing processing and wait state are added
Bus Cycle Definition
● M/I0#- memoryor Input/Output (output)
○ Distinguishes between memory and I/O cycles

○ The memory/ input-output is one of the primary bus cycle definition pins

■ 1 = memory cycle

■ 0 = input/output cycle

○ It is driven valid in the same clock as the ADS# signal is asserted

Bus Cycle Definition
● D/C - data or code (output)
○ Distinguishes between data and code or special cycles (control)

○ The data/code output is one of the primary bus cycle definition

pins.

■ 1=data

■ 0= code/ control.

○ It is driven valid in the same clock as ADS# signal is asserted

Bus Cycle Definition
● W/R# - write or read (output)
○ Distinguishes between write and read cycles

○ Write/read is one of the primary bus cycle definition pins

■ 1=write

■ 0=read

○ It is driven valid in the same clock as the ADS# signal is asserted

 Bus Cycle Definition
● Cache# cache ability (output)
○ Processor indication of internal cache ability.

○ The L1 cache must be enabled using the CD bit for CR0 for Cache# to be
asserted low

○ The cache# signal could also be described as the burst instruction signal,
because the cache# signal (qualified with KEN#) results in a burst mode
tranfer of 32 bytes of code or data.
 Bus Cycle Definition
● NA# - Next Address (input)

○ Indicates external memory is prepared for a pipeline

cycle
○ An active next address input indicates that the external
memory system is ready to accept a new bus cycle
although all data transfer for the current cycle have not
yet completed
Bus Cycle Definition
● Lock# - Bus Lock (output)
○ The bus luck pin indicates that the current bus cycle is locked,
typically for a read-modify-write operation.

○ The CPU will not allow a bus hold when Lock# is asserted

○ Locked cycles are generated when the programmer prefixes

certain instructions with the lock prefix
Cache Control
● KEN# Cache Enable (input)

○ Indicates to the pentium whether or not the system can

support a cache line fill for the current cycle.
○ Cache# ang Ken# are used together to determine if a
read will be turned into a linefill (burst cycle)
 Cache Control
● WB/WT# write-back/write-through (input)
○ This pin allows a cache line to be defined as a write-back or a
write-through on a line by line basis.
Bus Arbitration
● HOLD - Hold Bus (input)
○ Allows another bus master complete control of the CPU bus

○ In response to the bus hold request, the pentium processor will float most
of its output and input/output pins and asserts HLDA after completing all
outstanding bus cycles

○ Pentium processor will maintain its bus in its state until HOLD is de-
asserted.
 Bus Arbitration
● HLDA Bus Hold Acknowledge (output)
○ External indication that the pentium output are floated

● BOFF# Backoff (input)

○ Forces the pentium to get off the bus in next clock

○ After BOFF# is removed, the pentium restarts the bus cycle.

Bus Arbitration

● BREQ# Bus Request (output)

○ Indicates externally when a bus cycle pending
internally
○ Used to inform the arbitration logic that the pentium
need to control of the bus to perform a bus cycle
Interrupts
● INTR Maskable Interrupt (input)

○ Indicates that an external interrupt has been generated

○ If the IF( interrupt enable flag) bit in the EFLAGS

register is set, the pentium processor will generate two
locked interrupt acknowledge bus cycle ( to get type
number) and vectors to an interrupt handler after the
current instruction execution is completed.
Interrupts

● NMI - Non-Maskable Interrupt (input)

○ Indicates that an external non maskable interrupt
hasbeen generate
○ The pentium processor will vector to a type 2 interrupt
handler after the current instruction execution is
completed
Probe Mode
● R/S# - Resume/Stop [Run/Scan] (input)
○ The run/stop input is an asynchronous, edge-sensitive interrupt used to
stop the normal execution of the processor and place it into an idle state

● PRDY - Probe Ready (output)

○ The probe ready output pin indicates that the processor has stopped
normal execution in response to the R/S# pin going active. The CPU enter
the Probe Mode.