IMPLEMENTATION OF MULTIPLIER USING

FPGA FOR IMAGE PROCESSING APPLICATIONS

PROJECT GUIDE: Dr.N.Ramadass

TEAM MEMBERS:
Deepika VS (2016105025)
Meghana S Kanthadai (2016105041)
Nivethaa D (2016105564)
Pavithra A (2016105566)
 OBJECTIVE
• To implement a power and area efficient approximate multiplier in FPGA which uses
successive logarithmic converters for the realization of transcendental functions
in order to achieve complete elimination of “multiplication” for image processing
applications using Verilog.
 MOTIVATION
• Conventional arithmetic units focuses on maximizing speed of realizing but the
need for low power consumption is barely taken into account.

• 3D graphical processing units (GPUs) handle complex arithmetic calculations like

division, reciprocating, squaring, square-rooting, and exponentiation operations.

• They use most of the clock cycles => consume most power.

• Our multiplier is intended to overcome the problem of intense power consumption.

 INTRODUCTION

• In this project , we are implementing an approximate multiplier in

FPGA using Verilog.

• To lower power and increase speed , we sacrifice the accuracy of

multipliers.

• Precision is not required and do not make an obvious difference in

image processing due to perceptual limitations of humans.

• This multiplier uses successive logarithmic converters ,which

features complete elimination of multiplication.
• This approach reduces power consumption and it is area efficient.

• This multiplier manipulates the logarithmic arithmetic and improves the architecture
for realization of transcendental functions.

• All computations in image processing filters make use of transcendental functions

hence ,image processing filters can be implemented in FPGA with improved
efficiency for power and area and some tolerance for error.
 Input

BLOCK DIAGRAM
Raspberry pi Display

FPGA
Block Ram

Filters

Logarithmic
Arithmetic
unit(multiplier)
 FLOWCHART:
Obtain the error conversion coefficient values

Design the proposed log and antilog converters

using the conversion coefficients

Design modules for the other transcendental

functions like TRG ,exponential , log to any
base etc

Image processing Filters are designed using the

transcendental functions
Input image is fed to the FPGA and is filtered
using image processing filters in Verilog

Establish a serial interface with R-Pi to which

monitor is connected

Display the output image

Sample Architecture
 Proposed Architectures
Fixed-point format Qm.n of the x number
Proposed Architecture of
logarithmic arithmetic unit

Architecture of the proposed Architecture of the proposed

logarithmic converters antilogarithmic converters
THANK YOU