Dynamic CMOS

Design
Introduction
In static the output is connected to VDD or GND at any time
In dynamic the output is stored temporarily

Need for Dynamic CMOS design

◦ To reduce the no. of transistors
◦ Eliminates complementary pMOS
◦ Avoid static power consumption
Dynamic CMOS circuit
The pull down network is
constructed similar to static
CMOS

Dynamic CMOS Depends on

temporary storage of signal
values on the capacitance of
high impedance nodes.
Operations
There are two modes of operation
1.Precharge mode
2.Evaluation mode
 Precharge
When Clk=0, the output is precharged to VDD by pMOS
transistor.
 nMOS transistor is OFF and pulldown path is disabled.
 the evaluation FET eliminates any static power consumed
during precharge mode
 Evaluation Mode
When clk=1, precharge transistor Mp is OFF and evaluation transistor Me is ON.
The pull down path is enabled such that the output is discharged based on the input
values.
1.If PDN conducts (or) ON condition, then the output is discharged.
2.If PDN does not conduct (or) OFF condition, the precharged value is stored on the
output capacitance

Thus the output will be in high impedance in evaluation mode.

Properties of Dynamic Logic
 Logic function is implemented by PDN only
 Full swing outputs( VOL =GND, VOH = VDD )
 Non ratioed circuits (size is not important)
 Faster switching speeds due to reduced load capacitance.
Advantages
 Reduced no of transistors
 Occupies less area
 Synchronization is provided by clock signals
 Faster switching speed
 Glitching do not occur
Disadvantages
 Needs a precharge clock
 Power dissipation may increase
 Complex design
DOMINO LOGIC
The problem of faulty discharge of precharged nodes in CMOS dynamic circuits can be solved by
Domino circuits.
A single clock is sufficient to precharge and evaluate all gates within the block.
A domino logic consist of an n-type dynamic logic block followed by a static inverter.
During precharge - the output is charged to VDD, so the output of the inverter becomes zero.
During evaluation mode – the gate conditionally discharges and the ouput of inverter becomes
one.
ADVANTAGES DISADVANTAGES

Use smaller gates Each stage is buffered

Higher speed Only non inverted
Smooth operation structures are possible
Np domino Logic(NORA logic)
 To eliminate the need of an inverter
NP CMOS is used as an alternative approach

NP CMOS uses
1.n-tree
2.p-tree
out1

out2
In n-tree gates are controlled by clk, p-tree gates are
controlled by (clk)’
 Thus n-tree gates directly drive p-tree gates
During precharge:clk=0, out1 is charged to VDD
out2 is pre-discharged to 0
During evaluation:
output of n-tree make1to 0 and turning ON some transistors
in p-tree.
Zipper logic
 Zipper logic is a scheme for improving charge leakage and charge
sharing problems.
 Identical to NORA except the clock signals.
 Clock signals which drive pMOS precharge and nMOS discharge
transistors.
 pMOS pre-charge transistors gates are held at Vdd - |Vtp|
 nMOS pre-charge transistors gates are held at Vtn above GND.
Dual rail Domino logic
Each signal is encoded with a pair of wires.
The input and output signal pairs are denoted as Sig_h and Sig_l
Double rail domino
gate(inverter)
Dual rail domino for NAND/AND
All inverting and non inverting logic functions can be implemented
using double rail domino
When one PDN is ON and the other will be OFF
MULTIPLE OUTPUT DOMINO
LOGIC
Sequential Circuit Design
STATIC LATCHES AND REGISTERS:
Static latches use positive feedback so that the bistable circuit can be formed
Two inverters connected in cascade to form bistable circuit