Under the guidance of Prof.

V N Ramakrishnan

Group members :

1. Sonal Gawande (17MVD0051)

2. Aishwarya A Nair (17MVD0089)
3. Blessy Cherian (17MVD0008)
 Parasiticcapacitances are an integral part of any
device structure.

 They are unwanted capacitances and affect the

performance of the device and the circuit as a whole.

 Parasiticcapacitances result from the process of

device creation as well as their structure.
 Due to the scaling of CMOS devices, parasitic
capacitances have become a major constraint in the
correct operation.

 The increases in parasitic resistance and capacitance

from the transistor are expected to negatively affect
various aspects of overall circuit performance

 It is necessary to model these parasitic capacitances.

 We have used Sentaurus TCAD to model the devices

as well as to find intrinsic capacitances.
CSB = CDB = WECja + (W+2E) Cjp + WCjpg
Uniform doping concentration in the channel
and the source/drain.

No junctions.

Simpler process flow.

 PARAMETERS VALUES
GATE /CHANNEL 18nm
LENGTH
THRESHOLD 0.6V
VOLTAGE (VTH)
DRAIN DOPING 1E+18/cube
CONCENTRATION centimetre
(n-type)
SOURCE DOPING 1E+18/cube
CONCENTRATION centimetre
(n-type)
SUBSTRATE 1E+16/cube
DOPING centimetre
CONCENTRATION (p-type)
 Drain capacitance Gate capacitance

Source capacitance Body capacitance

 PARAMETERS VALUES
GATE /CHANNEL 18nm
LENGTH
THRESHOLD 0.3049V
VOLTAGE (VTH)
DRAIN DOPING 1E+18/cube
CONCENTRATION centimetre
(n-type)
SOURCE DOPING 1E+18/cube
CONCENTRATION centimetre
(n-type)
SUBSTRATE 1E+16/cube
DOPING centimetre
CONCENTRATION (p-type)