Ultra Low-Power High-Speed

Single-Bit Hybrid Full Adder Circuit

Guided by:
S J Vinaya
Assistant professor
Presented by:
Pooja S (1SI17EC410)
Shilpashree G (1SI17EC416)
Soundarya R (1SI17EC418)
Thushara C S (1SI17EC422)
2/4/2020 Dept. EC 1
Contents
 Introduction.
 Motivation and Objective.
 Literature Survey.
 Problem definition.
 Proposed Full Adder.
 Operation of the proposed Full Adder.
 Performance analysis of proposed Adder.
 4-bit ripple carry Adder.
 Conclusion.
 References.
2/4/2020 Dept. EC 2
Introduction
 As the technology and time advances the demand of low power and
fast operating devices is increasing.
 Full adder is the basic arithmetic circuit which is used in almost all
algorithms.
 Static full adders show more reliability and simplicity with lesser
energy requirement, but the on chip area requirement is usually
more as compared to dynamic logic based adders [1], [2].
 Complimentary CMOS, dynamic CMOS, CPL, TGA are the main
conventional logic designs [1],[2].
 Layout simulations are done using Cadence Virtuoso tools in 180-
nm technology.

2/4/2020 Dept. EC 3
Motivation
 CMOS weak inverters improve the power consumption.
 Pass transistors overcome voltage degradation problem.
 Carry logic is designed using transmission gates which reduces the
carry propagation path.

Objective
 The main objective of this project is to study the energy efficiency of Full
adder using various logic styles with a decreasing input voltage in 180-nm
technology.

2/4/2020 Dept. EC 4
Literature Survey
Sl. Title of the paper Remarks
No.
1 Manoj Kumar and R.K • In this paper, Carry logic is
Baghel, “Ultra Low-Power designed using transmission gates
High-Speed Single-Bit which reduces the carry
Hybrid Full Adder Circuit”. propagation path.
• The power and delay parameters
of the proposed single-bit full
adder are 930.3-nW and 43.07-ps
respectively.

2 Megha R and Vishwanath B • The objective of this paper is to

R, “Performance analysis of a investigate the power and delay
low-power high-speed hybrid performances of low voltage full
1bit full adder circuit using adder cells in different CMOS
CMOS technologies using logic styles.
cadence”.
2/4/2020 Dept. EC 5
 • Operating voltage, power
consumption decreases when
technology shrinks.

3 Subodh Wairya, Rajendra • Adder circuits are designed over

Kumar Nagaria, and the conventional CMOS, TG,
Sudarshan Tiwari, and hybrid adder circuits in
“Performance Analysis of terms of power, delay, power
High Speed Hybrid CMOS delay product (PDP), and energy
Full Adder Circuits for Low delay product (EDP).
Voltage VLSI Design.

4 Subodh Wairya, Rajendra • The static Majority function

Kumar Nagaria, and (bridge) design style enjoys a
Sudarshan Tiwari, “New high degree of regularity and
design methodologies for symmetric higher density than
high-speed mixed-mode the conventional CMOS design
CMOS full adder circuits”. style as well as lower power
consumption by using bridge
transistors.
2/4/2020 6
• This technique helps in reducing
power consumption, propagation
delay, and area of digital circuits
while maintaining low
complexity of mixed mode logic
designs.

2/4/2020 Dept. EC 7
Problem definition

 The problem being faced is designing of a Hybrid FA using Cadence

virtuoso 180-nm, 90-nm and 45-nm technology is to reduce delay, area and
power of a circuit.
 In the literature survey it is evident that the CCMOS logic utilizes 28-
Transistors, similarly in the CPL and TGA Logic uses 32T and 20T.
 The main drawbacks of CPL and TGA structures are voltage degradation in
the output voltage levels and slow response, high power utilization and
high area occupied.
 Therefore with the concern on power, area and speed, design and develop a
hybrid full adder structure and validation of these structures in 180nm
technology.

2/4/2020 Dept. EC 8
Proposed Full Adder

Fig. 1: Basic structure of a Full Adder

 The proposed structure basically contains 3 modules.
 Module 1 and 2 XNOR logics which are responsible for the sum
function.
 Module 3 is a carry module.
 𝑠𝑢𝑚 = 𝐴 ⊕ 𝐵 ⊕ 𝐶
𝐶𝑜𝑢𝑡 = AB + B𝐶𝑖𝑛 + 𝐶𝑖𝑛 A
= 𝐶𝑖𝑛 (A ⊕ B) + AB 2/4/2020 ………………………….(1) 9
Dept. EC
Contd.
• Proposed XNOR module

Fig. 2: XNOR circuit

 XNOR module is designed such that power consumption is less [3].
 The propose XNOR module uses 6T in different manner and the
proposed circuit consumes less power.
2/4/2020 Dept. EC 10
 Contd.
Proposed carry module

Fig. 3: Carry generating module

 Carry signal is mainly responsible for the delay of the proposed full
adder circuit [1].
 Reduction in the carry propagation path reduces the delay of carry
signal. 2/4/2020 Dept. EC 11
 Operation of the proposed Full Adder

𝑠𝑢𝑚 = 𝐴 ⊕ 𝐵 ⊕ 𝐶
𝐶𝑜𝑢𝑡 = AB + B𝐶𝑖𝑛 + 𝐶𝑖𝑛 A
= 𝐶𝑖𝑛 (A ⊕ B) + AB

If A=B, then 𝐶𝑜𝑢𝑡 = B

else 𝐶𝑜𝑢𝑡 = 𝐶𝑖𝑛

2/4/2020 Dept. EC 12
Contd.

Fig. 4: Complete diagram of proposed Full Adder

2/4/2020 Dept. EC 13
 Performance Analysis of Proposed Adder
 As W/L ratio of a transistor is varied, the power consumption also
varies accordingly [1], [2].
Power Analysis
 Total power consumption of a digital CMOS circuit is the sum of
dynamic, static and short circuit power.
 Dynamic power is the main source of power consumption in the
proposed full adder circuit design [4].
𝑃𝑡𝑜𝑡𝑎𝑙 = 𝑃𝑑𝑦𝑛𝑎𝑚𝑖𝑐 + 𝑃𝑠𝑡𝑎𝑡𝑖𝑐 + 𝑃𝑠𝑐
𝑃𝑑𝑦𝑛𝑎𝑚𝑖𝑐 = 𝑉𝑑𝑑 𝐹𝑐𝑙𝑜𝑐𝑘 σ𝑛𝑖 ∝𝑖 𝑉𝑖𝑠𝑤𝑖𝑛𝑔 𝐶𝑖𝑙𝑜𝑎𝑑 …………. (2)
Where,
𝐹𝑐𝑙𝑜𝑐𝑘 is representing the clock frequency of the system.
𝑉𝑖𝑠𝑤𝑖𝑛𝑔 is the voltage swing at intermediate nodes from 𝑖 to 𝑛.
𝐶𝑖𝑙𝑜𝑎𝑑 is the load capacitance at node 𝑖.
2/4/2020 Dept. EC 14
Delay Calculation
 Propagation delay is the time taken by the carry module to generate
the output signal.
 The delay propagation path is reduced by deploying strong
transmission gates.

Fig. 5: (a) R-C Equivalent of Transmission gate which causes delay, (b) R-C
Equivalent of m-stage cascaded.
2/4/2020 Dept. EC 15
Cont…

The total delay (given by 𝑡𝑝𝑑 𝑚 ) of m-cascaded stages can be

represented by Elmore’s Delay model [3] as follows
𝑚(𝑚+1)
𝑡𝑝𝑑 𝑚 = 0.69 [𝑅(𝐶1 +𝐶2 ) 2
+ 𝑚𝑅(𝐶𝐿 − 𝐶1 )] …………. (3)

𝑡𝑝𝑑 𝑚 total = 𝑡𝑝𝑑 𝑚 + 𝑡𝑝𝑑𝑏𝑢𝑓

𝑚(𝑚+1)
= 0.69 [𝑅(𝐶1 +𝐶2 ) +𝑚𝑅 (𝐶𝑖𝑛𝑏𝑢𝑓 − 𝐶1 )] + 𝑡𝑝𝑑𝑏𝑢𝑓 …….. (4)
2

Where 𝑡𝑝𝑑𝑏𝑢𝑓 is the delay of buffers, which is constant.

To get the optimum number of cascaded stages, differentiating the
average delay equation (4) with respect to m.

2/4/2020 Dept. EC 16
4-bit ripple carry Adder

Fig. 6: Building block diagram of 4-Bit Ripple Carry Adder

 In an RCA the output carry is forwarded to the next stage as an

input carry.
 The 4 bit RCA was designed using four single bit proposed adders
in umc 180nm environment.
2/4/2020 Dept. EC 17
Conclusion
 An ultra low power high speed full adder is emphasized using
modified XNOR modules.
 The design is also verified for 4-Bit ripple carry adder.
 New full adders designed using hybrid-CMOS design style with
pass transistor are presented in this paper that targets low PDP.

2/4/2020 Dept. EC 18
References
 N. H. E. Weste, D. Harris, and A. Banerjee, CMOS VLSI Design:A
Circuits and Systems Perspective, 3rd ed. Delhi, India: Pearson
Education, 2006.
 J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated
Circuits: A Design Perspective, 2nd ed. Delhi, India: Pearson
Education,2003.
 M. Vesterbacka, “A 14-transistor CMOS full adder with full
voltageswing nodes,” in Proc. IEEE Workshop Signal Process. Syst.
(SiPS),Taipei, Taiwan, Oct. 1999, pp. 713–722.
 S. Wairya, R. K. Nagaria, and S. Tiwari, “New design methodologies
for high-speed low voltage 1 bit CMOS Full Adder circuits,”
International Journal of Computer Technology and Application, vol. 2,
no. 3, pp. 190–198, 2011.
 Subodh Wairya, Rajendra Kumar Nagaria, and Sudarshan Tiwari,
“Performance Analysis of High Speed Hybrid CMOS Full Adder Low
Voltage VLSI Design,” VLSI Design,vol. 2012, Article ID 173079, 18
pages, 2012.

Dept. EC 19
2/4/2020 Dept. EC 20