MD MANAN MUJAHID

Research Scholar
Dept. of Electronics & Communication
Engineering
 Introduction

 Problem Definition

 Research Question

 Research Methodology

 Refernences
 Voltage scaling has become one of the most
effective techniques to reduce system energy
consumption.
 In order to minimize energy consumption while
maintaining the same target throughput, one
of the most promising approaches is to
increase the number of pipeline stages .
 The increased number of pipeline stages
increases the overhead due to latches and flip-
flops in terms of delay and energy, making the
performance of flip-flops critical at low
supply voltages
 In this paper we evaluate the performance of
different flip-flop designs operating at ultra
low voltages and make contributions in
determining the selections of ultra-low
voltage flip-flops based on performance
requirements. In flip-flop design metrics are
reviewed and the experimental setup is
introduced.
 In this paper, we present the novel
techniques that exploit special properties of
DSP systems to reduce the energy
consumption.
 challenging in we present a way of
implementing flip-flop additional
functionalities , usually added in standard-
cells library, in the pulse generator, thus
providing a robust and energy-efficient
pulse-triggered flip-flop
 This studies and develops pulse-triggered flip-
flops with the aimof pushing them in ultra-low
voltage operations. In addition to the
robustness challenge, ULV operations are
focusing on theenergy-efficiency of the
circuits.In order to explain the targets followed
all over this work, let us remind that
theenergy-delay product (EDP) is the main
figure of merit for UWVR circuits, whilethe
energy per operation (Eop) is of primary
importance in ULP applications.

 The research will be based on theory-assigned design and applied to
practical situations. Simulation will be used to design and analyze the system
according to the scenario. The proposed research will be carried out by
following phases

 Phase1 Survey
Study of different possible ultra low voltages, for delay, energy and energy-
delay product(EDP). With decreasing supply voltage, a pulse-triggered flip-
flop and a sense-amplifier based flip-flop produce smaller increase in setup
time, compared with a master-slaver flip-flop.

 Phase 2
 Study of possible solutions for Razor was to purposely operate the circuit at
the sub-critical voltage and reduce the operating voltage by analyzing the
error rate.

 Phase 3
 Study of Different possible ways of the proposed gated D flip-lop has uses
in pass
 transistor and transmission gates unlike CMOS gated flip-flop like Clocked
Pair Shared Flip flop (CPSFF).
 CPSFF is a gated flip-flop which ensure efficient and robust implementation
of low power sequential element, it uses less number of clocked transistor
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