https://ecee.colorado.edu/~bart/book/book/chapter6/ch6_3.

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tm#6_3_2
The general expression for the drain current equals the total charge in the inversion layer divided
by the time the carriers need to flow from the source to the drain

where Qinv is the inversion layer charge per unit area, W is the gate width, L is the gate length
and tr is the transit time. If the velocity of the carriers is constant between source and drain, the
transit time equals:

where the velocity, v, equals the product of the mobility and the electric field:
 The constant velocity also implies a constant electric field so that the field equals the
drain-source voltage divided by the gate length.

Now assume that the charge density in the inversion layer is constant between
source and drain. assume that the charge density in the inversion layer
equals minus the product of the capacitance per unit area and the gate-to-
source voltage minus the threshold voltage:
The inversion layer charge is zero if the gate voltage is lower than the
threshold voltage. Replacing the inversion layer charge density in the
expression for the drain current results the linear model:
The quadratic model uses the same assumptions as the linear model. However, this
model allows the inversion layer charge to vary between the source and the drain.

The derivation is based on the fact that the current is continuous throughout the
channel. The current is also related to the local channel voltage, > I >VC.

We now consider a small section within the device with width dy and channel
voltage VC + VS. The linear model as discussed still applies to such section ,so

On integrating
The drain current first increases linearly with the applied drain-to-source voltage, but
then reaches a maximum value.
The current would even decrease and eventually become negative.
The charge density at the drain end of the channel is zero at that maximum and changes
sign as the drain current decreases.
The charge in the inversion layer does go to zero and reverses its sign as holes are
accumulated at the interface. However, these holes cannot contribute to the drain current
since the reversed-biased p-n diode between the drain and the substrate blocks any flow
of holes into the drain.
The current reaches its maximum value and maintains that value for higher drain-to-
source voltages. A depletion layer located at the drain end of the gate accommodates the
additional drain-to-source voltage. This behavior is referred to as drain current
saturation.

The saturation occurs to the right of the dotted line which is given
by ID = m Cox W/L VDS2.
The Variable depletion layer model:
includes the variation of the charge in the depletion layer between the source
and drain. This variation is caused by the voltage variation along the channel.
The inversion layer charge is still given by:

where we now include the implicit dependence of the threshold voltage on

the charge in the depletion region

The voltage VC is the difference between the voltage within the channel and
the source voltage. We can now apply the linear model to a small section at a
distance y from the source and with a thickness dy. The voltage at that point
equals VC + VS while the voltage across that section equals dVC. This results
in the following expression for the drain current, ID:
Both sides of the equation can be integrated from the source to the drain with y varying from 0 to
the gate length, L, and the channel voltage, VC varying from 0 to the drain-source voltage, VDS. This
results in:

On integerating
Again, it was assumed that the drain current saturates at its maximum value, since a positive inversion
layer charge cannot exist in an n-type MOSFET. The drain voltage at which saturation occurs is given
by:
How to Calculate the Threshold voltage of a MOSFET

Base formula:

Vt=Vt-mos +Vfb

Vt-mos is the ideal threshold voltage (no work function difference between the gate and substrate materials)
and Vfb is the flatband voltage.

Vt-mos=2Φb+Qb/Cox where Cox= eox/tox

Φb=kT/q ln(NA/ni) where kT/q=.26mV at room temperature (300οK)

k=1.38x10-23 J/οK Boltzmann’s constant
T is the temperature in kelvins
q=1.602x10-19 Coulombs, the electron charge
NA=density of doped carriers (given)
ni=1.45x1010cm3 carriers in intrinsic silicon
eox=3.9x8.85x10-14 F/cm2, tox is given
Vsb is substrate bias (given)

Qb=√(2*esi *q* NA*(2*Φb+|Vsb|)) where esi=1.06x10-12 F/cm permittivity of silicon

The complete formula so far where Vsb = 0:

Vt-mos=2 kT/q ln(NA/ni) + √(2esiqNA2 Φb)*1/(eox/tox) (this is Vt0 in formula 2.30 3rd ed.
Also, his γ is Qb/Cox and Φs=2Φb)

Note: Vt-mos is positive for nMOS and negative for pMOS.

The flatband formulas:

Vfb=Φms-Qfc/Cox where Φms is work function difference ‘twn gate and wafer
Qfc is a fixed charge for surface states (given)

Φms=-(Eg/2±Φb) where sign is determine by the following rule:

+ if device is an nMOS
- if device is a pMOS
Eg is band gap energy of silicon… 1.1eV or…

Eg=(1.16-.704x10-3(T2/(T+1108)) (for silicon band gap energy at other than

room temp)

Vfb= -((1.16-.704x10-3(T2/(T+1108)))/2± kT/q ln(NA/ni))-Qfc/(eox/tox)

The entire Vt formula:

Vt=2 kT/q ln(NA/ni) + √(2esiqNA2 Φb)/(eox/tox)-((1.16-.704x10-3(T2/(T+1108)))/2± kT/q ln(NA/ni))-

 Derivation of MOSFET Threshold Voltage from the MOS

The threshold voltage equals the sum of the flatband voltage, twice the bulk
potential and the voltage across the oxide due to the depletion layer charge,
 Substrate bias effect: The voltage applied to the back contact affects the
threshold voltage of a MOSFET.
The voltage difference between the source and the bulk, VBS changes the
width of the depletion layer and therefore also the voltage across the oxide
due to the change of the charge in the depletion region. This results in a
modified expression for the threshold voltage, as given by:

The threshold difference due to an applied source-bulk voltage can therefore be

expressed by: