• 1. NET TYPES.

• 2. OPERATORS.

• 3. CONTINUOUS SIGNAL ASSIGNMENTS.

• 4. REFERENCES.
• Verilog data types are divided into two main groups: nets and
variables.

• A variable data type generally represents a piece of storage.

• It holds a value assigned to it until the next assignment.

example reg.

• A net data type represents a physical connection between

structural entities such as between gates or between
modules.

• It does not store any value. example tri, wand, supply0.

• Syntax

• Description
• Examples
• The System Verilog operators are a combination
of Verilog and C operators. In both languages, the
type and size of the operands is fixed.

• Verilog does not have increment and decrement

operators.

• System Verilog includes the C assignment

operators, such as +=, and the C increment and
decrement operators, ++ and --.
ASSIGNMENT OPERATORS:
In addition to the simple assignment operator, =,
SystemVerilog includes the C assignment operators and
special bitwise assignment operators.
• ARITHMETIC OPERATORS:
Arithmetic operators perform arithmetic operation on
signals and variables.
• LOGICAL OPERATOR:
Logical operators perform logical operations on signals
and variables. SystemVerilog added two new logical operators logical
implication (->), and logical equivalence (<->). -> is logically equivalent to
(!expression1 || expression2), <-> is logically equivalent to ((expression1 ->
expression2) && (expression2 -> expression1)).
• BITWISE OPERATORS:
The Verilog bitwise operators are used to perform a bit-
by-bit operation on two inputs. They produce a single output.
They take each bit individually and perform a Boolean algebra
operation with the other input.
• REDUCTION OPERATORS:
The reduction operators are used to convert vectors to
scalars. They operate on all of the bits in a vector to convert the
answer to a single bit.
• SHIFT OPERATORS:
The shift operator in Verilog is used to shift data in a
variable. The left hand side of the operator contains the variable
to shift, the right hand side of the operator contains the number
of shifts to perform.
OPERATORS PRECEDENCY:
Highest precedence
()
++ --
& ~& | ~| ^ ~^ ~ >< -
(unary)

*/%
+-
<< >>
< <= > >= in !in dist
=?= !?= == != === !==
& &~
^ ^~
| |~
&&
||
?:
= += -= *= /= %=
<<= >>= &= |= ^= ~&= ~|= ~^=

Lowest precedence
• FORMAL DEFINITION
Continuous assignments are the most basic assignment in
dataflow modeling. Continuous assignments are used to model
in combinational logic.

• SIMPLIFIED SYNTAX
net [strength] [range] [delay] identifier = net or register ;
assign [strength] [delay] net = net or register ;

• EXAMPLE
wire out;
assign out = In_A & In_B ;
Continuous assignment 'out' is a net. Both In_1 and In_2 are nets.

assign #25 out = In_A & In_B ;

Delay specification in the continuous assignment statement.
IMPORTANT NOTES

• Continuous assignments cannot be used within initial or

always blocks.

• Continuous assignment statements can be used on a net that

has been previously declared

• Only one net declaration assignment can be used for a net.

• More than one continuous assignment statement can be

made to a net.
• Stuart Sutherland “RTL Modeling With
SystemVerilog for Simulation and Synthesis: Using
SystemVerilog for Asic and Fpga Design’’.

• Chris spear, System Verilog for Verification: A Guide

to Learning the Test bench Language Features.