Lec - 04 - 05 - FET & FET Amplifiers

Field Effect Transistor
Amplifiers
Electronic Devices, 9th edition © 2012 Pearson Education. Upper Saddle River, NJ, 07458.
Thomas L. Floyd All rights reserved.
The FET
The idea for a field-effect transistor (FET) was first
proposed by Julius Lilienthal, a physicist and inventor. In
1930 he was granted a U.S. patent for the device.
His ideas were later refined and
developed into the FET. Materials
were not available at the time to
build his device. A practical FET
was not constructed until the
1950’s. Today FETs are the most
widely used components in
integrated circuits.
Introduction of FET
• FETs (Field-Effect Transistors) are much like BJTs (Bipolar Junction
Transistors).
• FETs sometimes called unipolar transistor operates only with one type
charge carrier.
• The two main types of FETs are JFET (Junction Field Effect
Transistor)
MOSFET (Metal Oxide
Semiconductor Field Effect
Transistor)
i. D-MOSFET –– Depletion MOSFET
ii. E-MOSFET –– Enhancement MOSFET
• The terms ‘Field Effect’ relates to the depletion region formed in the
channel of a FET as a result of a voltage applied on one of its
terminal(gate).
Similarities:
• Amplifiers
• Switching devices
• Impedance matching circuits
Differences:
FET BJT
• Unipolar device – operate use • Bipolar device – operate use both
only one type of charge carrier electron & hole
• voltage controlled devices • current controlled devices
• higher input impedance • higher gains
• FETs are less sensitive to temperature variations and because of there

construction they are more easily integrated on ICs.
• FETs are also generally more static sensitive (faster when turn on and
off ) than BJTs.
• FETs are usually smaller than BJTs and particularly useful for IC
chips.
(a) Current-controlled and (b) voltage-controlled amplifiers.
BJT – current controlled, IC is direct FET – voltage controlled, ID is a direct

function of IB function of the voltage VGS applied to the
input circuit.
There are two types of JFET : n-channel
and p-channel
JFET Symbol
The JFET
The JFET (or Junction Field Effect Transistor) is a normally
ON device. For the n-channel device illustrated, when the
drain is positive with respect to the source and there is no
gate-source voltage, there is current in the channel.
RD
When a negative gate voltage is
applied to the FET, the electric D
field causes the channel to n

+
G
p p VDD
narrow, which in turn causes –
– n
current to decrease. VGG
+ S
• The channel width and the channel resistance can be
controlled by varying the gate voltage – controlling the
amount of drain current, ID.
• The depletion region (white area) created by reverse

bias.
• Wider toward the drain-end of the channel – reverse-bias
voltage between gate and drain is greater than voltage
between gate and source.
• JFET operation can be compared to a water spigot.
The source of water pressure is the

accumulation of electrons at the
negative pole of the drain-source
voltage.
The drain of water is the electron

deficiency (or holes) at the positive
pole of the applied voltage.
The control of flow of water is the

gate voltage that controls the width of
the n-channel and, therefore, the flow
of charges from source to drain.
Basic Operation of JFET
The JFET
As in the base of bipolar transistors, there are two types of
JFETs: n-channel and p-channel. The dc voltages are
opposite polarities for each type.
RD
The symbol for an n-channel JFET is
shown, along with the proper polarities of Drain
+
the applied dc voltages. For an n-channel Gate VDD
device, the gate is always operated with a –
– Source
negative (or zero) voltage with respect to VGG
+
the source.
The JFET
There are three regions in the characteristic curve for a JFET
as illustrated for the case when VGS = 0 V.
Between A and B is the Ohmic ID
region, where current and voltage Ohmic region

are related by Ohm’s law. B VGS = 0 C
IDSS
From B to C is the active (or

constant-current) region where
current is essentially independent
of VDS.
Beyond C is the breakdown Active region
(constant current)
Breakdown
A VDS
region. Operation here can 0 VP (pinch-off voltage)
damage the FET.

The JFET
When VGS is set to different values, the relationship between
VDS and ID develops a family of characteristic curves for the
device. I D
An n-channel
IDSS VGS = 0
characteristic is
illustrated here.
Notice that Vp is VGS = –1 V
positive and has

VGS = –2 V
the same
magnitude as VGS = –3 V
VGS(off). VGS = – 4 V
VGS = VGS(of f) = –5 V
VDS
VP = +5 V
Summary
The JFET
A plot of VGS to ID is called the transfer or transconductance
curve. The transfer curve is a plot of the output current (ID)
to the input voltage (VGS). I D
The transfer curve is based on the IDSS

equation
2
 VGS 
I D  I DSS 1  
 V
 GS(off)  IDSS
2
By substitution, you can find other IDSS

4
points on the curve for plotting the
universal curve. –VGS
VGS(off) 0.3 VGS(off) 0
0.5 VGS(off)
Summary
The JFET
A certain 2N5458 JFET has IDSS = 6.0 mA and VGS(off) = – 3.5 V.

(a) Show the values of the
ID
these end points on the
transfer curve. IDSS = 6.0 mA
(b) Show the point for the

case when ID = 3.0 mA.
3.0 mA
(b) When ID = ½ IDSS,

VGS = 0.3 VGS(off). –VGS
0
Therefore, VGS = 1.05 V VGS(off) = 3.5 V 1.05 V
Summary
The JFET
The transconductance is the ratio of a change in output
current (DID) to a change in the input voltage (DVGS).
DI D
This definition is g m  ID
DVGS
The following approximate formula IDSS
is useful for calculating gm if you

know gm0.
 VGS 
g m  g m0 1   DID
 V
 GS(off)  DVGS
The value of gm0 can be found

–VGS
from 2 I DSS 0
gm0  VGS(off)
VGS(off)
Summary
The JFET
Because the slope changes at every point along the curve,
the transconductance is not constant, but depends on where
it is measured. I (mA) D
10 mA
What is the transconductance for 8.0

the JFET at the point shown? 6.0 5.7
4.0 3.7
DI D 5.7 mA  3.7 mA
gm   2.0
DVGS 0.7 V  (1.3 V)
–VGS
2.0 mA 4 3 2 1 0
  3.33 mS
0.6 V 1.3 0.7
Summary
JFET Input Resistance

VGS
The input resistance of a JFET is given by: RIN 
I GSS
where IGSS is the current into the reverse biased gate.
JFETs have very high input resistance, but it drops when the temperature
increases.
Compare the input resistance of a 2N5485 at 25 oC and at 100 oC.

The specification sheet shows that for VGS = 20 V, IGSS – 1 nA at 25
oC and 0.2 mA at 100 oC.
V 20 V
At 25 oC, RIN  GS   20 GW!
I GSS 1 nA
VGS 20 V
At 100 oC, RIN    100 MW
I GSS 0.2 μA
JFET Biasing
Self-bias is simple and effective, so it is the most common
biasing method for JFETs. With self bias, the gate is
essentially at 0 V. +V = +12 V DD
An n-channel JFET is illustrated. The current

in RS develops the necessary reverse bias that
RD
forces the gate to be less than the source. 1.5 kW
VG = 0 V
Assume the resistors are as shown and the
drain current is 3.0 mA. What is VGS? + IS
RG RS 330 W
1.0 MW –
VG = 0 V; VS = (3.0 mA)(330 W) = 0.99 V
VGS = 0 – 0.99 V =  0.99 V
JFET Biasing
You can use the transfer curve to obtain a reasonable value
for the source resistor in a self-biased circuit.
I D (mA)
What value of RS should you use 10 mA

to set the Q point as shown?
8.0
6.0
The Q point is approximately at Q 4.0
ID = 4.0 mA and VGS = 1.25 V.
2.0
VGS 1.25 V
RS    375 W –VGS
ID 3.0 mA 4 3 2 1 0
JFET Biasing
Voltage-divider biasing is a combination of a voltage-divider
and a source resistor to keep the source more positive than
the gate. +V DD
VG is set by the voltage-divider and is independent

RD
of VS. VS must be larger than VG in order to
R1 ID
maintain the gate at a negative voltage with
respect to the source. VG
VS IS
Voltage-divider bias helps stabilize the bias for
R2 RS
variations between transistors.
JFET Biasing
A graphical analysis of voltage-divider biasing is illustrated.
A typical transconductance curve for the 2N5485 is shown
with IDSS = 6.5 mA and VGS(off) = 2.2 V. +V DD
+12 V
Start with VG: ID (mA)
The Q-point
VG = 2.79 V
8.0 is read from R1 RD
VG/RS = 2.79 mA the plot. It is 3.3 MW 820 W
6.0
Connect the 3.3 mA and 2.79 V 2N5485
points to Q 4.0 0.7 V.
establish the
load line. 2.0 R2 RS
1.0 MW 1.0 kW
–VGS VGS
3 2 1 0 +1 +2 +3
Summary
JFET Ohmic Region

As described before, the ohmic region is between the
origin and the active region. A JFET operated in this
region can act as a variable resistor.
7
Data from an actual FET is Ohmic VG = 0 V
6
region
shown. The slopes (which
5
represent conductance) of VG =  0.5 V
ID 4
successive VGS lines are (mA)
VG = 1.0 V
different in the ohmic region. 3
This difference is exploited VG = 1.5 V

2
for use as a voltage 1
controlled resistance.
0
0 1 2 3 4 5 6 7 8
VDS (V)
Summary
JFET Ohmic Region

Here is a circuit in which the JFET is used as a variable
resistor. Notice that that the drain is connected through a
capacitor, which means the JFET’s Q-point is at the origin.
VCC
+15 V
The gain of the
BJT depends on RC
R1 3.9 kW Vout
56 kW
the dc voltage C1
Q1
setting of VGG. 1.0 µF
2N3904 C2
Vs = R2 10 µF R3
400 mV pp 39 kW RE Q2
100 k W VGG
1.0 kHz 6.2 kW 2N5458
Summary
The MOSFET
The metal oxide semiconductor FET uses an insulated gate
to isolate the gate from the channel. Two types are the
enhancement mode (E-MOSFET) and the depletion mode
(D-MOSFET). E-MOSFET
Drain RD
An E-MOSFET has no ID
channel until it is induced by Induced

SiO2
a voltage applied to the gate, n channel n
–
so it operates only in +
+ – +
Gate p substrate VDD
+ –
enhancement mode. An n- + –
–
channel type is illustrated n + n

VGG
here; a positive gate voltage –
induces the channel. Source
Summary
The MOSFET
The D-MOSFET has a channel that can is controlled by the
gate voltage. For an n-channel type, a negative voltage
depletes the channel; and a positive voltage enhances the
channel. D-MOSFET RD RD
A D-MOSFET can
operate in either n n
mode, depending on –
–
+
+
+
+
–
–
+ +
the gate voltage. –
–
+
+
p
–
VDD
+
+
–
– p
–
VDD
– + + –
– + + –
– +
VGG n VGG n
+ –
operating in D-mode operating in E-mode

Summary
The MOSFET
MOSFET symbols are shown. Notice the broken line
representing the E-MOSFET that has an induced channel.
The n channel has an inward pointing arrow.
E-MOSFETs D-MOSFETs
D D D D
G G G G
S S S S
n channel p channel n channel p channel
Summary
The MOSFET
The transfer curve for a MOSFET is has the same parabolic
shape as the JFET but the position is shifted along the x-axis.
The transfer curve for an n-channel E-MOSFET is entirely in
the first quadrant as shown. I D
The curve starts at VGS(th), which is a

nonzero voltage that is required to have
channel conduction. The equation for
the drain current is
I D  K VGS  VGS(th) 
2
0 VGS(th) +VGS
Summary
The MOSFET
Recall that the D-MOSFET can be operated in either mode.
For the n-channel device illustrated, operation to the left of
the y-axis means it is in depletion mode; operation to the
right means is in enhancement mode. I D
As with the JFET, ID is zero at VGS(off).

When VGS is 0, the drain current is
IDSS, which for this device is not the
maximum current. The equation for I DSS
drain current is
2
 V 
I D  I DSS 1  GS 
 V 
 GS(off)  –VGS
VGS(off) 0
Summary
MOSFET Biasing
E-MOSFETs can be biased using bias methods like the BJT
methods studied earlier. Voltage-divider bias and drain-
feedback bias are illustrated for n-channel devices.
+V DD +VDD
RD RD
R1 RG
R2
Voltage-divider bias Drain-feedback bias

Summary
MOSFET Biasing
The simplest way to bias a D-MOSFET is with zero bias. This
works because the device can operate in either depletion or
enhancement mode, so the gate can go above or below 0 V.
+VDD +VDD
RD RD
C
VG = 0 V IDSS ac
input
VGS = 0
RG RG
Zero bias, which can only be used for the D-MOSFET

JFET AMPLIFIERS
Summary
The Common-Source Amplifier
In a CS amplifier, the input signal
is applied to the gate and the output
+VDD
signal is taken from the drain. The
amplifier has higher input
resistance and lower gain than the RD
C3
Vout
equivalent CE amplifier. C1
RL
Vin RG RS C2
The voltage gain is given by the equation Av = gmRd.
Summary
Recall that conductance is the reciprocal of resistance and admittance

is the reciprocal of impedance. Data sheets typically specify the
forward transfer admittance, yfs rather than transconductance, gm. The
definition of yfs is DI
y fs  D
DVG
DYNAMIC CHARACTERISTICS Symbol Min Typ Max Unit

Forward Transfer Admittance 2N5457 |Yfs| 1000 3000 5000 m mhos
(VDS = 15 Vdc, VGS = 0) 2N5458 1500 4000 5500
An alternate gain expression for a CS amplifier is Av = yfsRd.
Summary
The Common-Source Amplifier ID (mA)
9
You can estimate what the transfer
characteristic looks like from values on
the specification sheet, but keep in mind
that large variations are common with
JFETs. For example, the range of 2
specified values for a 2N5458 is shown. – VGS (V)

–7 –1 0
OFF CHARACTERISTICS Symbol Min Typ Max Unit

Gate-Source Cutoff Voltage 2N5457 V GS(off) -0.5 - -6.0 Vdc
(VDS = 15 Vdc, iD = 10 nAdc) 2N5458 -1.0 - -7.0
ON CHARACTERISTICS Symbol Min Typ Max Unit

Zero Gate-Source Drain Current 2N5457 I DSS 1.0 3.0 5.0 mAdc
(VDS = 15 Vdc, VGS = 0) 2N5458 2.0 6.0 9.0
Summary
To analyze the CS amplifier. you need to start with dc values. It is useful

to estimate ID based on typical values; specific circuits will vary from
this estimate.
VDD
+12 V
For a typical 2N5458, what is
RD
the drain current? 2.7 kW
C1 Vout
2N5458
From the specification sheet, the 0.1 mF
Vin
typical IDSS = 6.0 mA and VGS(off) 100 mV RG RS C2
= 4 V. These values can be 10 MW 470 W 10 mF
plotted along with the load line

to obtain a graphical solution.
See the following slide…
Summary
(continued)
A graphical solution is illustrated.
On the transconductance curve, ID (mA)
plot the load line for the source
resistor.
Load line for 470 W resistor
6
Then read the current and
voltage at the Q-point.
Q 2.8 mA
ID = 2.8 mA and
VGS = 1.3 V
– VGS (V)
–4 0
1.3
2 V
Alternatively, you can obtain ID using Equation 9-2:  I D RS 
I D  I DSS
© 2012
1 
 Pearson Education.
 Upper Saddle River, NJ, 07458.
Electronic Devices, 9th edition
All rights V
 reserved.
GS(off) 
Thomas L. Floyd
Summary

Assume IDSS is 6.0 mA, VGS(off) is 4 V, and VGS = 1.3 V as
found previously. What is the expected gain?
Output is
inverted
VDD
2 I DSS 2  6.0 mA  +12 V
gm0    3.0 mS
VGS(off) 4 V RD
2.7 kW
 V 
g m  g m 0 1  GS  C1 Vout
 V 
 GS(off)  2N5458
0.1 mF
 1.3 V 
 3.0 mS 1   Vin
 4.0 V  100 mV RG
10 MW
RS
470 W
C2
10 mF
2.02 mS
Av = gmRd = (2.02 mS)(2.7 kW) = 5.45
Summary
The D-MOSFET
In operation, the D-MOSFET has the unique property in that it can be
operated with zero bias, allowing the signal to swing above and below
ground. This means that it can operate in either D-mode or E-mode.
ID
ent
em
nc
ha
+VDD
En
Q
RD C2
Vout
n Id
tio
C1 p le
e
D
RL –VGS 0 +VGS
Vin RG
Vgs
Summary
The E-MOSFET
The E-MOSFET is a normally off device. The n-channel device is biased
on by making the gate positive with respect to the source. A voltage-
divider biased E-MOSFET amplifier is shown.
ID
Enhancement
+VDD
Q
RD IDQ
C3
R1 Vout
C1 Id
RL VGS
0 VGS(th)
Vin C2
R2 RS
Vgs
VGSQ
Summary
The E-MOSFET
The E-MOSFET amplifier in
Example 9-8 is illustrated in
Multisim using a 2N7000 MOSFET.
Summary
The Common-Drain Amplifier +VDD
In a CD amplifier, the input signal C1

is applied to the gate and the output Vin C2
Vout
signal is taken from the source.
There is no drain resistor, because RG RS RL
it is common to the input and

output signals.
The voltage gain is always < 1, but the power gain is not.
Summary
The Common-Gate Amplifier
In a CD amplifier, the input signal

is applied to the source and the
output signal is taken from the
Drain. CG has a low input
resistance
The voltage gain is same as for common source amplifier
Summary
The Cascode Amplifier
Cascode amplifier is a two stage circuit
consisting of a transconductance
amplifier followed by a buffer
amplifier. The word “cascode” was
originated from the phrase “cascade to
cathode”. This circuit have a lot of
advantages over the single stage
amplifier like, better input output
isolation, better gain, improved
bandwidth, higher input impedance,
higher output impedance, better
stability, higher slew rate etc. The
reason behind the increase in
bandwidth is the reduction of Miller
effect.
Summary
The Cascode Amplifier
The cascode connection is a

combination of CS and CG
amplifiers. This forms a good
high-frequency amplifier.
Summary
The Class-D Amplifier
MOSFETs are useful as class-D amplifiers, which are very efficient

because they operate as switching amplifiers. They use pulse width
modulation, a process in which the input signal is converted to a series
of pulses. The pulse width varies proportionally to the amplitude of the
input signal.
Pulse-width modulation is easy to set up in Multisim. The

following slide shows the circuit. A sine wave is compared to a
faster triangle wave of the about the same amplitude using a
comparator (a 741 op-amp can be used at low frequencies).
Summary

A circuit that you can use Op-amp set
in lab or in Multisim to up as a
observe pulse width comparator
modulation in action. The
scope display is shown on
the following slide…
Summary

The signal is the yellow sine wave and is compared repeatedly to the
triangle (cyan). The result of the comparison is the output
(magenta).
The modulated signal is amplified
by class-B complementary
+VDD
MOSFET transistors. The output
is filtered by a low-pass filter to
recover the original signal and Q1
remove the higher modulation

Modulated
frequency. input Low-pass
filter
PWM is also useful in control
applications such as motor RL
Q2
controllers. MOSFETs are widely
used in these applications because
of fast switching time and low on- –VDD
state resistance.

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Field Effect Transistor

• FETs are less sensitive to temperature variations and because of there

BJT – current controlled, IC is direct FET – voltage controlled, ID is a direct

field causes the channel to n

• The depletion region (white area) created by reverse

The source of water pressure is the

The drain of water is the electron

The control of flow of water is the

region, where current and voltage Ohmic region

From B to C is the active (or

damage the FET.

positive and has

The transfer curve is based on the IDSS

By substitution, you can find other IDSS

A certain 2N5458 JFET has IDSS = 6.0 mA and VGS(off) = – 3.5 V.

(b) Show the point for the

(b) When ID = ½ IDSS,

is useful for calculating gm if you

The value of gm0 can be found

What is the transconductance for 8.0

JFET Input Resistance

Compare the input resistance of a 2N5485 at 25 oC and at 100 oC.

An n-channel JFET is illustrated. The current

What value of RS should you use 10 mA

VG is set by the voltage-divider and is independent

JFET Ohmic Region

This difference is exploited VG = 1.5 V

JFET Ohmic Region

channel until it is induced by Induced

channel type is illustrated n + n

induces the channel. Source

operating in D-mode operating in E-mode

The curve starts at VGS(th), which is a

As with the JFET, ID is zero at VGS(off).

Voltage-divider bias Drain-feedback bias

Zero bias, which can only be used for the D-MOSFET

The voltage gain is given by the equation Av = gmRd.

The Common-Source Amplifier

Recall that conductance is the reciprocal of resistance and admittance

DYNAMIC CHARACTERISTICS Symbol Min Typ Max Unit

An alternate gain expression for a CS amplifier is Av = yfsRd.

The Common-Source Amplifier ID (mA)

specified values for a 2N5458 is shown. – VGS (V)

OFF CHARACTERISTICS Symbol Min Typ Max Unit

ON CHARACTERISTICS Symbol Min Typ Max Unit

The Common-Source Amplifier

To analyze the CS amplifier. you need to start with dc values. It is useful

plotted along with the load line

The Common-Source Amplifier

The Common-Source Amplifier

In a CD amplifier, the input signal C1

it is common to the input and

The Common-Gate Amplifier

In a CD amplifier, the input signal

The voltage gain is same as for common source amplifier

The Cascode Amplifier

The cascode connection is a

The Class-D Amplifier

MOSFETs are useful as class-D amplifiers, which are very efficient

Pulse-width modulation is easy to set up in Multisim. The

The Class-D Amplifier

The Class-D Amplifier

remove the higher modulation