MOS Technology

• n-MOS fabrication & p-MOS fabrication

• CMOS Fabrication Process
– N-well process
– P-well process
– Twin tub process
• Stick diagrams
• Mos layers
• Layout and DRC
n-mos fabrication
*p-MOS fabrication process steps are similar to the above.
 Complementary MOS fabrication
• CMOS Technology depends on using both N-Type and P-Type devices on the
same chip.
• The two main technologies to do this task are:

– P-Well (Will discuss the process steps involved with this technology)

• The substrate is N-Type. The N-Channel device is built into a P-Type well within
the parent N-Type substrate. The P-channel device is built directly on the
substrate.

– N-Well

• The substrate is P-Type. The N-channel device is built directly on the substrate,
while the P-channel device is built into a N-type well within the parent P-Type
substrate.
• Two more advanced technologies to do this task are:

– Twin Tub

• Both an N-Well and a P-Well are manufactured on a lightly doped N-type

substrate.

– Silicon-on-Insulator (SOI) CMOS Process

• SOI allows the creation of independent, completely isolated nMOS and

pMOS transistors virtually side-by-side on an insulating substrate.
CMOS N-well process
CMOS N-well process
CMOS N-well process
CMOS N-well process
CMOS N-well process
CMOS N-well process
CMOS N-well process
CMOS N-well process
 CMOS N-well process

An N-well process is also widely used

Vin
P+ for P-substrate
contact) Vdd Vout Vss N+ (for N-
substrate
contact)

N-well
N+ N channel P+
Device P channel
Device
P-type substrate
 P-well on N-substrate

Steps :
• N-type substrate
• Oxidation, and mask (MASK 1) to create P-well (4-5m deep)
• P-well doping

P-well acts as substrate for nMOS devices.

The two areas are electrically isolated using thick field oxide.

SiO2

P-well

N-type substrate
 Polysilicon Gate Formation
Steps :
• Remove p-well definition oxide
• Grow thick field oxide
• Pattern (MASK 2) to expose nMOS and pMOS active regions
• Grow thin layer of SiO2 (~0.1m) gate oxide, over the entire chip surface
• Deposit polysilicon on top of gate oxide to form gate structure
• Pattern poly on gate oxide (MASK 3)

Thin gate Gate (patterned

oxide (SiO2) polysilicon on thin
oxide)

Thick
field nMOS active region
oxide P
pMOS active region N-type substrate
pMOS N+ Source/Drain difusion – self-aligned to Poly gate

Implant N+ pMOS S/D regions (MASK 5 – often the inverse of

MASK 4)

N+ implant/diffusion

N+ mask

P+ N+ P

N-type substrate
 pMOS N+ Source/Drain difusion, contact holes & metallisation

• Oxide and pattern for contact holes (MASK 6)

• Deposit metal and pattern (MASK 7)
• Passivation oxide and pattern bonding pads (MASK 8)
• P-well acts as substrate for nMOS devices.
• Two separate substrates : requires two separate substrate connections
• Definition of substrate connection areas can be included in MASK 4/MASK5

Vin

Vout
N+ for N-substrate Vdd Vss
P+ (for P-
contact) substrate
contact)
P
P+ P channel N+
Device N channel
Device
N-type substrate
Twin-Tub (Twin-Well) CMOS Process