A TEACHER- STUDENT CONVERSATION ON

“CMOS FABRICATION PROCESS FLOW”

 Let’s Start!!
• We try to address three foundational
questions through out the ppt.
• Rest is simple just some steps in a sequence.
 N.B.- don’t care about spelling or front of letters

• Teacher : We are going to learn cmos fabrication

technology, students.
• Students: we already knew it sir.
• Teacher: How?
Studets: This one!!
Teacher: NO, we want them on a same
crystal!!!!

• Students: Why?????????????????????
• Students: So exactly we have to learn??
• Teacher: just some steps?
• Students: ok that’s it??
• Teachers: no, connect them
logically>>>>>>>>>>with proper algorithm
for cost i.e. money which is a tool to exploit
people :3 , think like a communist.
• Students: Why???????
• Teacher: we have three different process flow
• All of them will give cmos.
• P well
• N well
• Twin well/tub
• Student : why not only one, sir??
 Those who paved the path
Frank Wanlass & Andrew Grove from Fairchild
Semiconductor
FIG: MIT LINCOLN LABRORATORY : Some HIGH END
MICROELECTRONICS FABRICATION TAKing place
PLACE
 Through out the slides different type
of oxides are used a summary of them
NEW LET US SEE THE LOGICALLY
CONNECTED STEPS ONE AFTER
ANOTHER
 Need of well:
• As pmos and nmos must be fabricated over
same crystal and as each one reuires different
substrate like n sub for pmos and p sub for n
mos , so we can use p sub with n well or n sub
with p well or lightly doped sub with both well
N WELL PROCESS
Step 1. take p type substrate
 Step 2: oxidation
• Purpose is to protect certain regions of the
wafer from n type diffusion for well formation
Step 3: Applying photoresist
 Step 4: Photolithography
• To open window where n well will form
Step 5: Etching of SiO2
Step 6: Remove PR
 Step 7: N well formation
• Well will act as substrate of n mos
Step 8: Resultant structure after Sio2
removal
 Step 9: Self alligned Gate formation
• 1. Eliminate the need of alignment of gate with source drain
2. reduce overlap capacitance 3. mask for doping of source
and drain
 More on self allined gate
• Fabricate gate first
 Due to the inevitable misalignment of the gate mask with respect to the source
and drain mask, it was necessary to have a fairly large overlap area between the
gate region and the source and drain regions, to ensure that the thin-oxide
region would bridge the source and drain, even under worst-case misalignment.
This requirement resulted in gate-to-source and gate-to-drain parasitic
capacitances that were large and variable from wafer to wafer, depending on the
misalignment of the gate oxide mask with respect with the source and drain
mask. The result was an undesirable spread in the speed of the integrated
circuits produced, and a much lower speed than theoretically possible if the
parasitic capacitances could be reduced to a minimum. The overlap capacitance
with the most adverse consequences on performance was the gate-to-drain
parasitic capacitance, Cgd, which, by the well-known Miller effect, augmented
the gate-to-source capacitance of the transistor by Cgd multiplied by the gain of
the circuit to which that transistor was a part. The impact was a considerable
reduction in the switching speed of transistors.
In 1966, R.W. Bower realized that if the gate electrode was defined first, it would
be possible not only to minimize the parasitic capacitances between gate and
source and drain, but it would also make them insensitive to misalignment. He
proposed a method in which the aluminum gate electrode itself was used as a
mask to define the source and drain regions of the transistor. However, since
aluminum could not withstand the high temperature required for the
conventional doping of the source and drain junctions
Step 6: Poly silicon patterning
Step 7: field oxide formation
Step 8: Defining regions for source
drain
Step 9: n+ diffusion
Step 10: P mos source drain formation
• Student: finished???? we are bored.
• Teacher: wait, who will make contacts!! just
there.............
Step 11: Defining contact terminals
Step 12: metallization
Teacher: here we go!!!!!!!!
Teacher : there are some advantages and
disadvantages for n well. I will teach them at the
end while we compare three process
technologies.
• Student: now p well?? again 13 steps?? oh my
god!! will be bored...
• Teacher: i have a short cut. replace p with n
and n with p of n well process.....and then
magic!! we can get p well or for weaker
students let me discuss the p well again......
P well process technology
1. INTRINSIC SUBSTRATE DOPING(N TYPE)
2.OXIDATION
3. PHOTOLITHOGRAPHY AND ETCHING OF SILICON
DIOXIDE(MASK 1)
4.P WELL DIFFUSION(MASK 1)
5.FORMATION OF DIFFUSION AREA FOR PMOS(MASK 1)
6.DEPOSITION OF THIN OXIDE LAYER(THINOX)
7. DEPOSITION OF POLYSILICON LAYER
 8.DEPOSITION OF POLYSILICON
9.DEPOSITION OF ANOTHER LAYER OF PHOTORESIST
10. ETCHING FOR GATE FORMATION( MASK 2)
 9.DEPOSITION OF SILICON DIOXIDE FOR INSULATION.
10.GROWING OF ANOTHER PHOTORESIST LAYER FOR MAKING
SOURCE AND DRAIN IN PMOS.
11.FORMATION OF P+ DIFFUSION LAYER FOR PMOS.(MASK 3)
12. FORMATION OF N+ DIFFUSION LAYER FOR NMOS.(MASK 4)
13. ETCHING FOR MAKING CONTACT CUT(MASK 5)
14. Metalization
15. FINAL MASKING FOR REMOVING EXTRA
METAL(MASK 6)
 LIMITATIONS
• 1. LATCH UP DUE TO THE COMBINATION OF N-
WELL/P-WELL AND SUBSTRATE RESULTS IN THE
FORMATION OF PARASITIC N-P-N-P
STRUCTURES.
SOLUTION: SOI TECHNOLOGY
•2. SEPERATE OPTIMIZED WELL ARE NOT
AVAILABLE , INDEPENDENT OPTIMIZATION OF
GAIN THRESOLD VOLTAGE OF BOTH NMOS AND
PMOS IS NOT POSSIBLE.
SOLUTION :USE TWIN TUB
 ADVANTAGES
• LESS NO OF STEPS
• LESS COST AS ONLY 6 MASKS ARE REQUIRED.
THAN TWIN TUB
• Teacher : now twin tub...
• Student: ok... it’s sounds great...
• Teacher: yeah...but it’s bit costly...and you
know money is a tool..
• Student: yeah we know, you just continue with
twin tub.
TWIN TUB PROCESS TECHNOLOGY
STEP 1: PADOXIDE (THIN LAYER OF
SIO2) FORMATION.PADOXIDE WILL
PREVENT STRES
STEP 2: NITRIDE LAYER
FORMATION( NITRIDE WILL ACT AS
A MASK FOR OXIDATION)

During the growth of the immersed

insulating thermal oxide structures
(steps V and VI), the silicon nitride
layer (layer 3) is pushed upwards.
Without the buffer oxide (layer 2, also
known as pad oxide), this would
create too much tension in the Si
substrate (layer 1), the plastic
deformation would occur and the
STEP 3: NITRIDE ETCHING(MASK 1)
STEP 4: FIELD OXIDE FRMATION THICK
LAYER OF SIO2(LOCOS)
 STEP 5: FINAL STRUCTURE AFTER
REMOVAL OF NITRIDE AND PADOXIDE
STEP 6: P WELL FOMATION (MASK 2)
STEP 7: N WELL FORMATION(MASK 3)
STEP 9: POLY SILICON DOPING ( MASK
5)
STEP 10 : SOURCE DRAIN FORMATION
(MASK 5)
STEP 11: CONTACT FORMATION (MASK
6)
STEP 12: METALLIZATION( MASK 7)
STEP 13: OVERALL SURFACE
PASSIVATION ( MASK 8)
 CONCLUSION:
• ADVANTAGES: IT IS POSSIBLE TO MODULATION OF P WELL OR N MOS PERFORMANCE
WITHOUT COMPROMISING N WELL OR P MOS STRUCTURE.
DISADVANTAGES:
1. LATCH UP ( SHORT CIRCUIT BETWEEN N MOS OR P MOS AND SHORT BETWEEN VDD AND
GROUND ) .LATCH UP DUE TO THE COMBINATION OF N-WELL/P-WELL AND SUBSTRATE RESULTS
IN THE FORMATION OF PARASITIC N-P-N-P STRUCTURES.
PREVENTION: SILICON ON INSULATOR TECHNOLOGY
2. BIRDS BEAK FORMATION
When performing LOCOS steps for thermal oxidation growth, a bird's beak effect is commonplace. As the oxide
grows, the nitride mask, which is meant to block the oxide from growing everywhere, is slightly bent due to stress
caused by the oxide pushing the nitride as it grows.
Figure 6.4: Geometry of the bird's beak occurrence during LOCOS processing. and describe the maximum height
and length of the nitride after oxidation, respectively.
PREVENTION : SHALLOW TRENCH ISOLATION
3. NUMBER OF MASK IS HIGHER THAN N WELL AND P WELL PROCESS, SO COST IS HIGH
PREVENTION : NOTHING CAN BE DONE , CONSIDER AS PAY OFF!!!