Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Background
Swapping
Contiguous Memory Allocation
Paging
Structure of the Page Table
Segmentation
Example: The Intel Pentium
Operating System Concepts – 7th Edition, Feb 22, 2005 8.2 Silberschatz, Galvin and Gagne ©2005
Objectives
Operating System Concepts – 7th Edition, Feb 22, 2005 8.3 Silberschatz, Galvin and Gagne ©2005
Background
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Basic Hardware
Base and Limit Registers
A pair of base and limit registers define the logical address space
Operating System Concepts – 7th Edition, Feb 22, 2005 8.5 Silberschatz, Galvin and Gagne ©2005
Address binding
Binding of Instructions and Data to Memory
Operating System Concepts – 7th Edition, Feb 22, 2005 8.6 Silberschatz, Galvin and Gagne ©2005
Multistep Processing of a User Program
Operating System Concepts – 7th Edition, Feb 22, 2005 8.7 Silberschatz, Galvin and Gagne ©2005
Logical vs. Physical Address Space
Operating System Concepts – 7th Edition, Feb 22, 2005 8.8 Silberschatz, Galvin and Gagne ©2005
Memory-Management Unit (MMU)
Operating System Concepts – 7th Edition, Feb 22, 2005 8.9 Silberschatz, Galvin and Gagne ©2005
Dynamic relocation using a relocation register
Operating System Concepts – 7th Edition, Feb 22, 2005 8.10 Silberschatz, Galvin and Gagne ©2005
Dynamic Loading
Operating System Concepts – 7th Edition, Feb 22, 2005 8.11 Silberschatz, Galvin and Gagne ©2005
Dynamic Linking & shared libraries
Operating System Concepts – 7th Edition, Feb 22, 2005 8.12 Silberschatz, Galvin and Gagne ©2005
Swapping
Major part of swap time is transfer time; total transfer time is directly
proportional to the amount of memory swapped
Operating System Concepts – 7th Edition, Feb 22, 2005 8.13 Silberschatz, Galvin and Gagne ©2005
Schematic View of Swapping
Operating System Concepts – 7th Edition, Feb 22, 2005 8.14 Silberschatz, Galvin and Gagne ©2005
Contiguous Allocation
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HW address protection with base and limit registers
Operating System Concepts – 7th Edition, Feb 22, 2005 8.16 Silberschatz, Galvin and Gagne ©2005
Contiguous Allocation (Cont.)
Multiple-partition allocation
Hole – block of available memory; holes of various size are
scattered throughout memory
When a process arrives, it is allocated memory from a hole
large enough to accommodate it
Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
OS OS OS OS
process 8 process 10
Operating System Concepts – 7th Edition, Feb 22, 2005 8.17 Silberschatz, Galvin and Gagne ©2005
Dynamic Storage-Allocation Problem
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Fragmentation
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Address Translation Scheme
Operating System Concepts – 7th Edition, Feb 22, 2005 8.21 Silberschatz, Galvin and Gagne ©2005
(5*4)+0
Base add * size+offset
Operating System Concepts – 7th Edition, Feb 22, 2005 8.22 Silberschatz, Galvin and Gagne ©2005
Paging Hardware
Operating System Concepts – 7th Edition, Feb 22, 2005 8.23 Silberschatz, Galvin and Gagne ©2005
Paging Model of Logical and Physical Memory
Operating System Concepts – 7th Edition, Feb 22, 2005 8.24 Silberschatz, Galvin and Gagne ©2005
Paging Example
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Implementation of Page Table
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Associative Memory
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Paging Hardware With TLB
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Effective Access Time
Operating System Concepts – 7th Edition, Feb 22, 2005 8.30 Silberschatz, Galvin and Gagne ©2005
Memory Protection
Operating System Concepts – 7th Edition, Feb 22, 2005 8.31 Silberschatz, Galvin and Gagne ©2005
Valid (v) or Invalid (i) Bit In A Page Table
Operating System Concepts – 7th Edition, Feb 22, 2005 8.32 Silberschatz, Galvin and Gagne ©2005
Shared Pages
Shared code
One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window systems).
Shared code must appear in same location in the logical
address space of all processes
Operating System Concepts – 7th Edition, Feb 22, 2005 8.33 Silberschatz, Galvin and Gagne ©2005
Shared Pages Example
Operating System Concepts – 7th Edition, Feb 22, 2005 8.34 Silberschatz, Galvin and Gagne ©2005
Structure of the Page Table
Hierarchical Paging
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Hierarchical Page Tables
Operating System Concepts – 7th Edition, Feb 22, 2005 8.36 Silberschatz, Galvin and Gagne ©2005
Two-Level Page-Table Scheme
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Two-Level Paging Example
A logical address (on 32-bit machine with 1K page size) is divided into:
a page number consisting of 22 bits
a page offset consisting of 10 bits
Since the page table is paged, the page number is further divided into:
a 12-bit page number
a 10-bit page offset
Thus, a logical address is as follows:
12 10 10
where pi is an index into the outer page table, and p2 is the displacement
within the page of the outer page table
Operating System Concepts – 7th Edition, Feb 22, 2005 8.38 Silberschatz, Galvin and Gagne ©2005
Address-Translation Scheme
Operating System Concepts – 7th Edition, Feb 22, 2005 8.39 Silberschatz, Galvin and Gagne ©2005
Three-level Paging Scheme
Operating System Concepts – 7th Edition, Feb 22, 2005 8.40 Silberschatz, Galvin and Gagne ©2005
Hashed Page Tables
The virtual page number is hashed into a page table. This page
table contains a chain of elements hashing to the same location.
Operating System Concepts – 7th Edition, Feb 22, 2005 8.41 Silberschatz, Galvin and Gagne ©2005
Hashed Page Table
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Inverted Page Table
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Inverted Page Table Architecture
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Segmentation
Operating System Concepts – 7th Edition, Feb 22, 2005 8.45 Silberschatz, Galvin and Gagne ©2005
User’s View of a Program
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Logical View of Segmentation
4
1
3 2
4
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Segmentation Architecture
Operating System Concepts – 7th Edition, Feb 22, 2005 8.48 Silberschatz, Galvin and Gagne ©2005
Segmentation Architecture (Cont.)
Protection
With each entry in segment table associate:
validation bit = 0 illegal segment
read/write/execute privileges
Protection bits associated with segments; code sharing
occurs at segment level
Since segments vary in length, memory allocation is a
dynamic storage-allocation problem
A segmentation example is shown in the following diagram
Operating System Concepts – 7th Edition, Feb 22, 2005 8.49 Silberschatz, Galvin and Gagne ©2005
Segmentation Hardware
Operating System Concepts – 7th Edition, Feb 22, 2005 8.50 Silberschatz, Galvin and Gagne ©2005
Example of Segmentation
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Example: The Intel Pentium
Operating System Concepts – 7th Edition, Feb 22, 2005 8.52 Silberschatz, Galvin and Gagne ©2005
Logical to Physical Address Translation in
Pentium
Operating System Concepts – 7th Edition, Feb 22, 2005 8.53 Silberschatz, Galvin and Gagne ©2005
Intel Pentium Segmentation
Operating System Concepts – 7th Edition, Feb 22, 2005 8.54 Silberschatz, Galvin and Gagne ©2005
Pentium Paging Architecture
Operating System Concepts – 7th Edition, Feb 22, 2005 8.55 Silberschatz, Galvin and Gagne ©2005
Linear Address in Linux
Operating System Concepts – 7th Edition, Feb 22, 2005 8.56 Silberschatz, Galvin and Gagne ©2005
Three-level Paging in Linux
Operating System Concepts – 7th Edition, Feb 22, 2005 8.57 Silberschatz, Galvin and Gagne ©2005
End of Chapter 8