CMOS Digital Integrated Circuits

CHAP: 9
Dynamic Logic Circuits

1 CMOS Digital Integrated Circuits

 Dynamic Logic Circuits

 Goals
Understand
• Pass transistors circuits
• Voltage bootstrapping
• Synchronous dynamic circuit techniques
• Dynamic CMOS circuit techniques
• High-performance dynamic CMOS circuits

2 CMOS Digital Integrated Circuits

 Static v.s. Dynamic
 Static Logic Gates
• Valid logic levels are steady-state operating points
• Outputs are generated in response to input voltage levels after a certain
time delay, and it can preserve its output levels as long as there is power.
• All gate output nodes have a conducting path to VDD or GND, except when
input changes are occurring.
• This approach required a large number of transistor to implement function
 Dynamic Logic Gates
• Used in high density, high performance digital implementation where
reduction of ckt delay & silicon area is major objective.
• The operation depends on temporary storage of charge in parasitic node
capacitances.
• The stored charge does not remain indefinitely, so must be updated or
refreshed. This requires establishment of an update or recharge path to the
capacitance frequently enough to preserve valid voltage levels.

3 CMOS Digital Integrated Circuits

 Static v.s. Dynamic (Continued)

 Advantages of Dynamic Logic Gates

• Allow implementation of simple sequential circuits with memory
functions.
• Use of common clock signals throughout the system enables the
synchronization of various circuit blocks.
• Implementation of complex circuits requires a smaller silicon area
than static circuits.
• Often consumes less dynamic power than static designs, due to
smaller parasitic capacitances.

4 CMOS Digital Integrated Circuits

 Pass-Transistor Latch
Circuit and Operation
Soft note

Vx Q Q
D MP
X
Cx
CK

 Operation
• CK = H, D=H or L : CX is charged up or down through MP, and X
becomes H or L (depends on D input) since MP is on  D and X
are connected.
• CK = L: X is unchanged since MP is off and CX is isolated from D,
and the charge is stored on capacitances CX.
• For X = H, Q = L and Q = H
• For X = L, Q = H and Q = L
 Cost: very low
5 CMOS Digital Integrated Circuits
 Pass-Transistor Latch
Soft Node Concept
• During CK = 1: Let D = 1, i.e. VD = VOH = VDD MP is conducting
and charges CX to a “weak 1” (VX = VDD – VTN)  Q = L
(VQ<VTN) and Q = H(VQ=VDD).
• During CK = 0: Logic-level VX is preserved through charge storage
on CX. However, VX starts to drop due to leakage.
• What value does VX have to deteriorate to no longer like a stored ?
Example For an inverter with VDD = 5V, VT,n = 0.8V , VOH =5V ,
VOL = 0V and VIH = 2.9V, initial VX =4.2 V. But due to leakage
currents, this will decline over time. When it declines below
VIH(2.9V), then a logic 0 out of the inverter can no longer
guaranteed.
Thus, to avoid an erroneous output, the charge stored in CX must
be restored or refreshed to its original level before VX declines
below 2.9 V.

6 CMOS Digital Integrated Circuits

 Basic Principles of Pass Transistor Circuits
Logic “1” Transfer (charge up event)
 Logic “1” Transfer: VX(t=0)=0V, Vin=VOH=VDD, CK=0 VDD

Soft note


Vx ID Vx
Vin MP Vin=VDD D S
X MP X
Cx Cx
CK CK

• VGS = VDD - VX, VDS = VDD - VX = VGS.

• Therefore, VDS> VGS – VT,MP MP is in saturation.
dV X k n
V DD V X V T ,MP 
2
CX   
dt 2
• Note that the VT,MP is subject to substrate bias effect and therefore,
depends on the voltage level VX. We will neglect the substrate
bias effect for simplicity.

7 CMOS Digital Integrated Circuits

 Basic Principles of Pass Transistor Circuits
Logic “1” Transfer (Cont.)
• Integrating the above equation with t from 0  t and VX from 0 
VX, we have
t VX
2C X dV X
0 dt  
k n 0 V DD  V X  V T , MP 
2

VX
2C X 1

• Therefore, k n V DD  V X  V T , MP 0

2C X  1 1 
t   
kn  V DD  V X  V T ,MP V DD  V T ,MP 
• and,
k n V DD  V T , MP 
t
V X (t )  V DD  V T , MP 
2C X
k V  V T , MP 
1  n DD t
2C X
8 CMOS Digital Integrated Circuits
 Basic Principles of Pass Transistor Circuits
Logic “1” Transfer (Cont.)
VX
Vmax=VDD-VT,MP
Vmax

t
0
• VX rises from 0V and approaches a limit value Vmax = VX(t)|t= = VDD-VT,MP,
but it can not exceed this value, since the pass transistor will turn off at this
point (VGS=VT,MP). Therefore, it transfers a “weak logic 1”.
• The actual Vmax by taking the body effect into account is,

V max  V DD  V T 0,MP    2 F  V max  2 F 

• and tcharge = time to reach 0V to VX = 0.9Vmax,
2C X  1 1 
t charge    
kn  V DD  0.9V max  V T ,MP V DD  V T ,MP 
• Body Effect: Reduce VX, and Increase tcharge
9 CMOS Digital Integrated Circuits
 Basic Principles of Pass Transistor Circuits
Logic “0” Transfer (Charge Down Event)
 Logic “0” Transfer: VX(t=0)=Vmax= VDD – VT,MP, Vin=VOL=0V,
CK= 0  VDD
Soft note


Vx ID Vx
Vin MP Vin=0 S D
X MP X
Cx Cx
CK CK

• VGS = VDD, VDS = Vmax = VDD – VT,MP.

• Therefore, VDSVGS – VT,MP MP is in linear region.

dV X k n  
 CX  2 V DD  V T ,MP V X  V 2X 
dt 2
• Note that the VSB=0. Hence, there is no body effect for MP
(VT,MP= VT0,MP). But the initial condition VX(t=0)=VDD – VT,MP
contains the threshold voltage with body effect. To simplify the
expressions, we will use VT,MP in the following.
10 CMOS Digital Integrated Circuits
 Basic Principles of Pass Transistor Circuits
Logic “0” Transfer (Cont.)
• Integrating the above equation with t from 0  t and VX from
VDD - VT,MP  VX, we have

 1 1 
 
 2V DD  V T ,MP  2V DD  V T ,MP  
t VX VX
2C X dV X
0 dt   k n  2V DD  V T ,MP V X  V 2X     2V DD  V T ,MP   V X   V X  dVX
V DD V T ,MP V DD V T ,MP  

 
  2V DD  V T ,MP   V X 
VX
CX
 ln 
k n V DD  V T ,MP    VX  V DD V T ,MP

2V DD  V T ,MP 
• Therefore,
 2V DD  V T , MP   V X  and, V X (t ) 
t
CX
ln   V T , MP  / C X
  
k n V DD V T , MP  VX  1  etk n V DD

11 CMOS Digital Integrated Circuits

 Basic Principles of Pass Transistor Circuits
Logic “0” Transfer (Cont.)
• VX drops from Vmax = VDD-VT,MP, to 0V. Hence, unlike the charge-
up case, it transfers a “strong logic 0”.
• fall = time of VX drops from 0.9Vmax to 0.1Vmax,
 fall  t 90%  t10%

CX ln(19)  ln(1.22) VX
k n V DD  V T ,MP  Vmax=VDD-VT,MP
Vmax
CX
 2.74
k n V DD  V T ,MP 
• where,

CX  2  0.9 V DD  V T ,MP  

t 90%  ln 
k n V DD  V T ,MP   0.9 V DD  V T ,MP   0
t

 CX ln 1.22 
k n V DD  V T ,MP 
CX  1.9 
t10%  ln 
k n V DD  V T ,MP   0.1 
12 CMOS Digital Integrated Circuits
 Basic Principles of Pass Transistor Circuits
Charge Storage and Charge Leakage
• At t = 0, CK=0, VX= Vmax, Vin =0. The charge stored in CX will
gradually leak away, primarily due to the leakage currents
associated with the pass transistor. The gate current of the inverter
driver transistor is negligible.
Ileakage Vx Igate=0
Vin =0 MP

Cx
CK=0
VCK=0
Ileakage VX
Vin=0
CX
n+ Isubthreshol n+

p-type Si Ireverse

13 CMOS Digital Integrated Circuits

 Basic Principles of Pass Transistor Circuits
Charge Storage and Charge Leakage (Cont.)
VCK=0 Ileakage VX
Vin=0
n+ n+ CX
Isubthreshold
p-type Si Ireverse

Ileakage= Isubthreshold + Ireverse

Ileakage Vx

Cin= Cgb + Cpoly + Cmetal

Cj(VX) Cin
Isubthreshold Ireverse
CX= Cin + Cj
Drain-substrate pn-junction
• Isubthreshold is the subthreshold current for the pass transistor with CK=0.
• Ireverse is the reverse current for the source/drain pn junction at node X
• Cj (VX) : due to the reverse biased drain-substrate junction, a function of VX
• Cin: due to oxide-related parasitics, can be considered constants.
14 CMOS Digital Integrated Circuits
 Basic Principles of Pass Transistor Circuits
Charge Storage and Charge Leakage (Cont.)
Ileakage= Isubthreshold + Ireverse
Ileakage Vx

Cin= Cgb + Cpoly + Cmetal

Isubthreshold Cj Cin
Ireverse
CX= Cin + Cj

Drain-substrate pn-junction
• The total charge stored in the soft node can be expressed as,
Q = Qj (VX) + Qin where Qin = Cin•VX
• The total leakage current can be expressed as the time derivative
of the total soft-node charge Q
dQ
I leakage 
dt
dQ j (V X ) dQin
 
dt dt
dQ j (V X ) dV X dV X
  C in
dV X dt dt
15 CMOS Digital Integrated Circuits
 Basic Principles of Pass Transistor Circuits
Charge Storage and Charge Leakage (Cont.)
• Where
dQ j (V X )
 C j (V X )
dV X
AC j 0 AC j 0 SW
 
1 V X 1 V X
0  0 SW

kT  N D N A  kT  N D N ASW 
0  ln   0 SW  ln 
q  ni2  q  ni
2

• Therefore,
 
 
 AC j 0 AC j 0 SW  dV X
I leakage     C in 
 1 V X 1 V X  dt
 0  0 SW 
 
• We have to solve the above differential equation to estimate the
actual charge leakage time from the soft node.
16 CMOS Digital Integrated Circuits
 Voltage Bootstrapping
• The Voltage bootstrapping is a technique to overcome the threshold
voltage drops of the output voltage levels in pass transistor gates or
enhancement-load inverters and logic gates.
• Consider the following circuit with VXVDD  M2 is in saturation. If
Vin is low, the maximum output voltage is limited as
Vout(max) = VX – VT2(Vout)
VDD

Vx M2
Vout

Vin M1
Cout

17 CMOS Digital Integrated Circuits

 Voltage Bootstrapping (Cont.)
• To overcome the voltage drop, the voltage VX must be increased. This
can be achieved by adding a third transistor M3 into the circuit.
» CS and Cboot represent the capacitances which dynamically couple
VX to the ground and to the output.
» The goal of the above circuit is to provide a high enough voltage
VX to let Vout go to VDD instead of VDD-VT2(Vout).
VDD

M3
Vx
M2
CS Cboot Vout

Vin M1 Cout

• Initially, let Vin=H M1 and M2 are on, and Vout=L.

• Now Vin goes to L  M1 turns off, and Vout starts to rise. This change
will be coupled to VX through the bootstrap capacitor, Cboot.
18 CMOS Digital Integrated Circuits
 Voltage Bootstrapping (Cont.)
• Let iCboot be the transient current through Cboot during the charge-up event,
and let iCS be the current through CS. Assume iCS  iCboot, we have
iCS  iCboot CS·dVX/dt  Cboot·d(Vout-VX)/dt
 (CS+Cboot)·dVX/dt  Cboot·dVout/dt
 dVX/dt  Cboot /(CS+Cboot) ·dVout/dt
• This expression can be integrated to give VX such that Vout will rise to VDD.
C boot
V DD V T 3 dV X  C S  C boot V OL dV out
VX V DD

 V X  V DD  V T 3   V DD  V OL 
C boot
.
C S  C boot
• If Cboot >> CS, then for Vout rising to VDD,
VX(max)  2VDD – VT3 – VOL > VDD – VT2.
for realistic values of the voltages. Thus, it is feasible to use the circuit to
obtain Vout =VDD.

19 CMOS Digital Integrated Circuits

 Voltage Bootstrapping (Cont.)

• To overcome the threshold voltage drop at Vout, the minimum VX is

VX(min) = VDD + VT2|Vout = VDD
= [VDD-VT3(VX)]+Cboot /(CS+Cboot) ·(VDD-VOL)
• Therefore, the required capacitance ratio Cboot /(CS+Cboot) is
C boot V T 2 Vout VDD  V T 3 VX

C S  C boot V DD  V OL
C boot V T 2 Vout VDD  V T 3 VX
. 
C S V DD  V OL  V T 2 Vout VDD  V T 3 VX
• CS is the sum of the parasitic source-to-substrate capacitance of M3 and the
gate-to-substrate capacitance of M2.

20 CMOS Digital Integrated Circuits

 Voltage Bootstrapping (Cont.)
• Cboot can be specifically constructed to control its value by using a
transistor with the source and drain connected together at Vout and the gate
attached to VX. Since its drain and source tied together, it simply acts as an
MOS capacitor between VX and Vout.
VDD

M3
Vx
M2

Cboot
Vout
Vin M1

21 CMOS Digital Integrated Circuits

 Synchronous Dynamic Circuit Techniques –
Dynamic Pass Transistor Circuits
• The multi-stage synchronous circuit is shown below. The circuit consists
of cascaded combinational logic stages interconnected through nMOS
pass transistors. Its operation depends on temporary charge storage in the
parasitic input capacitances.

Comb. Comb. Comb. F1

A Logic Logic Logic
B 1 2 3 F2

1 C 2 D 1
1
t
2 phase1 phase2
t
1,2 non-overlapping clocks
• Logic levels are stored on input capacitances during the inactive clock
phase.
22 CMOS Digital Integrated Circuits
 Dynamic Pass Transistor Circuits
Two-Phase Clock Dynamic Shift Register
 Depletion-Load Dynamic Shift Register
• The max clock frequency is determined by signal propagation delay
through one inverter stage.
• One half-period of the clock signal must be long enough to allow Cin to
charge up or down, and Cout to charge to the new value.
• The logic-high input value is one VT0 lower than VDD.

VDD VDD VDD

1 2 1
Vout

Vin
Cin1 Cout1 Cin2 Cout2 Cin3 Cout3

23 CMOS Digital Integrated Circuits

 Dynamic Pass Transistor Circuits
Enhancement-Load Dynamic Shift Register
 Enhancement-Load Dynamic Shift Register 1
• Instead of biasing load transistors with a constant gate voltage, a clock
signal is applied to the gate of the load transistor  power dissipation
and silicon area are reduced.
• The power supply current flows only when the load devices are activated
by the clock signal, the power consumption is lower than the depletion-
load nMOS logic.

VDD VDD VDD

1 2 1
2

Vout

Vin
Cin1 Cout1 Cin2 Cout2 Cin3 Cout3

24 CMOS Digital Integrated Circuits

Enhancement-Load Dynamic Shift Register 1 (Cont.)
General Structure
VDD VDD
2 1
1
Z
A
nMOS nMOS
B Logic Logic
Stage 1 Stage 2
C D

General Circuit Structure of Ratioed Synchronous Dynamic Circuit

25 CMOS Digital Integrated Circuits

Enhancement-Load Dynamic Shift Register 1 (Cont.)
VDD VDD VDD
1=H 2 1
1 2
Vout1 Vout2
Vout3

Vin
Cin1 Cout1 Cin2 Cout2 Cin3 Cout3

Vout2VOL
VDD VDD VDD
2=H 2 1
1 2
Vout1 Vout2
Vout3

Vin
Cin1 Cout1 Cin2 Cout2 Cin3 Cout3
Vout1VOL Vout3VOL

• VOL → kdriver/kload Ratioed Dynamic Logic.

• Cout1, Cin2 & Cout2, Cin3 interact  Charge Sharing
26 CMOS Digital Integrated Circuits
 Enhancement-Load Dynamic Shift Register 2
 Enhancement-Load Dynamic Shift Register 2
• The input pass transistor and the load transistor are driven by the same
clock phase.
• The valid low-output voltage level VOL=0V can be achieved regardless of
the driver-to-load ratio, this circuit is a ratioless dynamic logic.

VDD VDD VDD

1 2 1

Vout

Vin
Cin1 Cout1 Cin2 Cout2 Cin3 Cout3

27 CMOS Digital Integrated Circuits

Enhancement-Load Dynamic Shift Register 2(Cont.)
General Structure
VDD VDD
1 2

Z
A
nMOS nMOS
B Logic Logic
Stage 1 Stage 2
C D

General Circuit Structure of Ratioless Synchronous Dynamic Circuit

28 CMOS Digital Integrated Circuits

Enhancement-Load Dynamic Shift Register 2 (Cont.)
1=H VDD VDD VDD
1 2 1
Vout1 Vout2
Vout3

Vin
Cin1 Cout1 Cin2 Cout2 Cin3 Cout3

Vout1VOL Vout2 0V Vout3VOL

2=H VDD VDD VDD
1 2 1

Vout1 Vout2
Vout3

Vin
Cin1 Cout1 Cin2 Cout2 Cin3 Cout3

Vout10V Vout2VOL Vout30V

• VOL → 0V Ratioless Dynamic Logic.
• Cini << Couti-1 for i=2,3  Minimum Charge Sharing
29 CMOS Digital Integrated Circuits
 Dynamic CMOS Transmission Gate Logic
• Each transmission gate is controlled by the clock signal and its
complement. Therefore, the two-phase clocking need four clock signals.
• As in the nMOS structures, the CMOS dynamic circuit relies on charge
storage in parasitic input capacitances during the inactive clock cycles.
1 2
1

B
F1

Stage 1
C Stage 2
D
1
1 2
31 CMOS Digital Integrated Circuits
 Dynamic CMOS Transmission Gate Logic
Shift Register
• The basic building block of the shift register consists of a CMOS
inverter, which is driven by a TG.
• CK=1Vin is transferred onto the parasitic input capacitance CX.
• The low on-resistance of TG results in
» A smaller transfer time compared to nMOS-only switches.
» No threshold voltage drop across TG

soft node VDD

CK

Vin VX Vout

CK CX Cy

32 CMOS Digital Integrated Circuits

 Dynamic CMOS Transmission Gate Logic
Shift Register (Cont.)
• The single-phase CMOS shift register is built by
» Cascading identical inverter units
» Driving each stage alternately with the CK and CK.
• Ideally: The odd-numbered stages are on as CK=1, while the even-
numbered stages are off  the cascaded inverter stages are
alternately isolated.
• Practically:
» The CK and CK are not a truly nonoverlapping signal pair,
since their waveforms have finite rise and fall times.
» One of the signals is generated by inverting the other  the
clock skew is unavoidable.
» True two-phase clocking is preferred over single-phase
clocking.
CK CK CK
V1 V2 V3 V4

CK CK CK
33 CMOS Digital Integrated Circuits
 Dynamic CMOS Precharge-Evaluate Logic
Reduced Transistor Count
VDD

 Mp
Vout
• =0  C precharges to
C VDD (output is not available
nMOS Internal during precharge)
inputs Logic capacitance •  =1  C selectively
discharges to 0 (output is
only available after
Me discharge is complete)

 evaluate

t
precharge precharge
Vout
t
34 CMOS Digital Integrated Circuits
 Dynamic CMOS Precharge-Evaluate Logic
An Example
VDD

 Mp
Vout

A1
B1
A2
B2
A3

Me

Z is high when =0

Z=(A1 A2A3 +B1B2)
35 CMOS Digital Integrated Circuits
 Dynamic CMOS Precharge-Evaluate Logic
Advantages/Disadvantages
 Advantages
• Need only N+2 transistors to implement a N-input gate.
• Low static power dissipation
• No DC current paths to place constraints on device sizing
• Input capacitance is same as pseudo nMOS gate.
• Pull-up time is improved by active switch to VDD.
 Disadvantages
• The available time of output is less than 50 % of the time.
• Pull-down time is degraded due to series active switch to 0.
• Logic output value can be degraded due to charge sharing with other gate
capacitances connected to the output.
• Minimum clock rate determined by leakage on C.
• Maximum clock rate determined by circuit delays.
• Input can only change during the precharge phase. Inputs must be stable
during evaluation; otherwise an incorrect value on an input could
erroneously discharge the output node. (single phase P-E logic gates can
not be cascaded)
• Outputs must be stored during precharge, if they are required during the
next evaluate phase.

36 CMOS Digital Integrated Circuits

 Dynamic CMOS Precharge-Evaluate Logic
Cascading Problem
VDD VDD
Mp1 precharge evaluate
 Mp2 
Vout1 Vout2
t
1st stage 2nd Vout1 does not switch from
nMOS Vout
inputs 1 “1” to “0” fast enough
Logic t
Vout correct state
Me2 erroneous state
Me1 t

• Evaluate:
» Me1, Me2  ON
» Mp1, Me2  OFF
• Problem: All stages must evaluate simultaneously one clock does
not permit pipelining of stages.
37 CMOS Digital Integrated Circuits
 High Performance Dynamic CMOS Circuits
Domino CMOS Logic
Static inverter serves to buffer the
logic part of the circuit from its
VDD VDD
output load

X Vout

nMOS
inputs Logic • =0
» X precharges to VDD, and Vout = 0.
• =1
» X remains high, and Vout remains
low.
 precharge evaluate » X discharges to 0, and Vout
1
changes from 0 to 1.
t

38 CMOS Digital Integrated Circuits

 Domino CMOS Logic
VDD VDD VDD


X1 X2 X3

nMOS nMOS nMOS

inputs Logic Logic Logic

 evaluate evaluate
precharge teval t
X1
t Max number gates limited:
X2
total propagation delay < teval
X3 t

t
39 CMOS Digital Integrated Circuits
 Domino CMOS Logic (Cont.)
VDD VDD VDD


X1 X2 X3

nMOS nMOS nMOS

inputs Logic Logic Logic

• The problem in cascading conventional dynamic CMOS occurs

when one or more inputs make a 1 to 0 transition during evaluation.
• Domino circuits can fix the above problem
» During the evaluation, each buffer output can make at most one
transition (from 0 to 1), and thus each input of all subsequent
logic stages can also make at most one (0 to 1) transition.

40 CMOS Digital Integrated Circuits

 Domino CMOS Logic
The Limitations

• The limitation: the number of inverting static logic stages in

cascade must be even, to let the inputs of next domino stage can
have only 0 to 1 transitions during the evaluation.
• Can implement only non-inverting logic
• Due to precharge use, can suffer from charge sharing during the
evaluation which may cause erroneous outputs.
» The problem will be described in the next slide, and several
solutions will be presented later.

41 CMOS Digital Integrated Circuits

 Domino CMOS Logic
Charge Sharing
VDD VDD

 VX
Vout
C1
N
C2
VX = VDDC1/(C1+C2)
Keep C2 << C1

• Assume that all inputs are low initially, and the voltage across C2=0V
• During the precharge, C1 is charged to VDD
• If transistor N switches from 0 to 1 during the evaluation phase, the
charge initially stored in C1 will be shared by C2. Therefore, the
value of VX will reduced.

42 CMOS Digital Integrated Circuits

 Domino CMOS Logic
Reduce Charge Sharing Degradation of VX

VDD
weak pull-up pMOS

VX Vout

nMOS
inputs Logic Push VX to VDD unless there
is a strong pull-down path
between Vout and ground

43 CMOS Digital Integrated Circuits

 Domino CMOS Logic
Reduce Charge Sharing Degradation of VX (Cont.)
VDD

 • Use separate pMOS transistors to

precharge all intermediate nodes in
VX1 Vout1 nMOS pull-down tree which have a
large parasitic capacitance.
nMOS C1 • Effectively eliminate all charge
Logic sharing problems during evaluation
VX2 Vout2 • Allow implementation of multiple-
output domino structures.
• Can cause additional delay since the
nMOS C2
nMOS tree need to drain a larger
Logic charge to pull down VX

Another Way: Use a smaller threshold voltage

 the final stage output is not affected by lowering of VX
trade off the pull-up speed (weaker pMOS transistor)
44 CMOS Digital Integrated Circuits
 Domino CMOS Logic
An Example of Multiple-Output Domino Circuits
VDD

C4
P4 G4
C3
P3 G3
C2
P2 G2
C1
P1 G1

C0
Reduce transistor count
• C1=G1+P1C0
• C2=G2+P2G1+P2P1C0
• C3=G3+P3G2+P3P2G1+P3P2P1C0
• C4=G4+P4G3+P4P3G2+P4P3P2G1+P4P3P2P1C0
45 CMOS Digital Integrated Circuits
 NORA CMOS Logic (NP-Domino Logic)
VDD VDD VDD

  

nMOS pMOS nMOS

Logic Logic Logic

to nMOS stage to pMOS stage

nMOS stage all stages nMOS stage all stages

precharge evaluate precharge evaluate
 pMOS stage pMOS stage
pre-discharge pre-discharge

• Advantages
» An Inverter is not required at the output of stages
» Allow pipelined system architecture
• Disadvantages: Also suffer from charge sharing and leakage

46 CMOS Digital Integrated Circuits

 NORA CMOS Logic (NP-Domino Logic)
Examples
VDD VDD VDD

  

• =L: nMOS precharges to H, and pMOS pre-discharges to L.

• =L→H: All cascaded nMOS and pMOS logic stages evaluate
one after the other.

47 CMOS Digital Integrated Circuits

Pipelined True Single-Phase Clock (TSPC) Dynamic CMOS
VDD VDD VDD VDD

 

nMOS pMOS
Logic  Logic to next N-block

N-block P-block
Using tristate inverters between stages decouples the stages and enables pipelined operation
• =L: nMOS blocks precharge to VDD
pMOS blocks evaluate by selective pull-up to VDD
• =H: pMOS blocks pre-discharge to VDD
nMOS blocks evaluate by selective pull-down to 0V
•  is not used, no clock skew problem can arise.
• Provide similar performance to NORA structure
48 CMOS Digital Integrated Circuits
 TSPC-Based Rising Edge-triggered D-type Flip-Flop
VDD VDD VDD VDD


 Q


D

• Need only 11 transistors.

• Static Edge Triggered D Flip-flop need 16 transistors.
 Common Advantages of dynamic Logic Styles
• Smaller area than fully static gates.
• higher speed: smaller parasitic capacitances.
• Glitch free operation if design carefully

49 CMOS Digital Integrated Circuits

 Summary

• Full complementary static logic is best option in the majority of

CMOS circuits.
» Noise-immunity is not sensitive to kn/kp
» Does not involve precharge of nodes
» Dissipate no DC power
» Layout can be automated
» Large fan-in gates lead to complex circuit structures (2N
transistors)
» Larger parasitics
» Slower and higher dynamic power dissipation than alternatives
» No clock

50 CMOS Digital Integrated Circuits

 Summary (Cont.)

• Pseudo-nMOS static logic finds widest utility in large fan-in

NOR gates.
» Require only N+1 transistors for N fan-in
» Smaller parasitics
» Faster and lower dynamic power dissipation than full CMOS
» Noise immunity sensitive to kn/kp
» Dissipate DC power when pulled down
» Not well suited for automated layout
» No clock

51 CMOS Digital Integrated Circuits

 Summary (Cont.)

• CMOS domino logic should be used for low-power, high speed

applications
» Require only N+k transistors for N fan-in, size advantages of
pseudo-nMOS.
» Dissipate no DC power
» Noise immunity is not sensitive to kn/kp
» Use of clocks enables synchronous operation
» Rely on storage on soft node
» Require exhaustive simulation at all the process corners to insure
proper operation
» Some of the speed advantage over static gates is diminished by
the required per-charge (pre-discharge) time.

52 CMOS Digital Integrated Circuits