Area Optimized Fpga Implementation of Color Edge Detection: Project Guide - Dept of ETC Group - B

Major Project Final Presentation (2019), Department of Electronics and Telecommunication Engg
AREA OPTIMIZED FPGA

IMPLEMENTATION OF COLOR EDGE
DETECTION
Project Guide –
Dr. Raghunandan Swain
Dept of ETC
Group – B
Project Coordinator – Head of Department –

Mr. Nawal Topno Mrs. T. Mita kumari
Assistant Professor, Dept of ETC Assistant Professor, Dept of ETC
Group –B
Members –
• Abhisek Samantaray(1501109338)
• Neekita Prusty(1501109353)
• Sasmita Kumari Gouda (1501109363)
Major Project Final Presentation(2019), Department of

Group - B 2
Electronics & Telecommunication Engg
Overview
• Introduction
• Past Work
• Current work
• Results
• Conclusion
• References

Group - B 3
Introduction
• An edge is an abrupt change in brightness of the pixels.
• Detecting edges is an important task\in boundary detection, motion detection/estimation,
texture analysis, segmentation, and object identification.
• Edge information for a particular pixel is obtained by exploring the brightness of pixels in
the neighbourhood of that pixel and mathematically analogous to calculating the
derivative of brightness.
• Different edge detection methods (Prewitt, Laplacian, Roberts, Sobel and Canny) use
different discrete approximations of the derivative function.

Group - B 4
Contd.
• For improved edge detection masks,the feature of parallelism works.
• FPGA can implement far larger logic functions & supports sufficient logic
to implement complete systems and sub-systems.
• FPGA provides designers with reconfigurable logic that can be
reprogrammed on application-specific basis.
• This drastically increases flexibility in the design process.

Group - 5
Past Work
• In 1977 Professor Ramakant Nevatia of USC published the first journal
paper (we think) on color edge detection, in which he extended the
Hueckel operator, developed 4 years previously, to color images. Since
then, at least 17 other journal papers.
• A method had been published for edge detection , which is called “Fusion
Detection”.

Group - 6
Contd.
1. Output fusion appears to be the most popular; the goal is to
perform edge detection three times, once each for red, green,
and blue (or whatever color space is being used), and then the
output is fused to form one edge map.How ever there are some
disadvantages for which we follow new method for edge
detection.

Group - 7
Need of Edge Detection
• Most of the shape information of an image is enclosed in edges. So first
we detect these edges in an image and by using these filters and then by
enhancing those areas of image which contains edges, sharpness of the
image will increase and image will become clearer.

Group - 8
Sobel Edge Detection Operator
• The Sobel Edge Detection Operator is a 3*3 spatial mask. It is based on the
differential operation [1 0 -1] and an averaging operator [1 2 1],convolving
these operators we get the 3*3 spatial mask for sobel.
-1 0 1 Horizontal Gradient Operator -1 -2 -1 Vertical Gradient
Operator
-2 0 2 0 0 0
-1 0 1 1 2 1
• The spatial mask is convolved over the image to obtain the edge.
local edge strength is defined as the gradient magnitude given by 1 ,
 1. GM ( x, y ) = Root over(Gx^ 2 + Gy^ 2)
Square and sqaure root operations are costly for every pixel in(1).
Group - B 2. GM ( x , y ) = | Hx
Major| Project
+Electronics
| Hy |
Final Presentation(2019), Department of
& Telecommunication Engg
9
Present Work

Group - B 10
System overview

Group - 11
Edge Detection Hardware Architecture
• The Block gives the overall I/O ports on the edge detect ion system using
FPGA.
• The bus_rw controls the direction of data transfer while data_strobe and
mode_strobe signals control the entire data transfer operation.
• The clk signal is the internal clock of the FPGA.

Group -B 12
Sobel Architecture
• P0,P1,P2,P3,P4,P5,P6,P7and P8 represents the eight bit pixel inputs to the sobel
module.
• The module consists of signed substractors, shift registers and module operators.
• The output of the final adder block will be 11bits.
• The output data is compared to limit the value to a max. of 255 as the output image is
also composed of 8-bit wide pixels.
• 32 sobel modules are used in parallel.The limitation on the number of parallel sobel
operators that can be implemented is logic resources available in the target device.

Group - 13
Contd…
• The sobel output for one group of pixels calculated as per |Gx| + |Gy|
where Gx and Gy are calculated from the formula given in here.

Group - 14
Software used
• MATLAB 7.5 : Used to model the whole system for an easy
understanding of hardware implementation of the algorithm.
• XILINX ISE 14.7 : Used for design , simulation and synthesis of hard
ware system model in verilog HDL. In Xilinx the target device used to
implement the design isxc3s1500-4fg676

Group - 15
Matlab Code For Converting Image To Text
• clc;
• close all;
• fid = fopen('input.txt');
• txtData = textscan(fid,'%s');
• txtData = cell2mat(txtData{1,1});
• textImage = zeros(row ,col , 3);

• for noI = 1:noImage
• idx = (noI - 1)*row*col +1:noI*row*col;
• tempData = txtData(idx, :);
• textImage(:,:,1) = reshape(hex2dec(tempData(:, 1:2)), col ,row)';
•
• figure, imshow(uint8(textImage));
•
• end

Group - B 16
Matlab Code For Verification Of Text To Image
• clc;
• close all;
• fid = fopen('input.txt');
• txtData = textscan(fid , '%s ');
• txtData = cell2mat(txtData{1,1});
• textImage = zeros(row ,col , 3);
• for noI = 1:noImage

• idx = (noI - 1)*row*col +1:noI*row*col;
• tempData = txtData( idx, :);
•
• figure, imshow(uint8(textImage));
•
Group
• -B
end 17
Sobel Core Module Verilog Code
• module sobel( p0, p1, p2, p3, p5, p6, p7, p8, out);
• input [7:0] p0,p1,p2,p3,p5,p6,p7,p8;
• output [7:0] out;
• wire signed [10:0] gx , gy ;
• wire signed [10:0] abs_gx , abs_gy ;
• wire [10:0] sum;
• assign gx=((p2-p0)+((p5-p3)<<1)+(p8-p6));
• assign gy=((p0-p6)+((p1-p7)<<1)+(p2-p8));
• assign abs_gx = (gx[10]? ~gx+1 : gx);
• assign abs_gy = (gy[10]? ~gy+1 : gy);
• assign sum = (abs_gx + abs_gy);
• assign out = (|sum[10:8])?8'hff : sum[7:0];
• endmodule

Group - B 18
Sobel Edge Detection Verilog Code:-
• module imageedge (bus, data_strobe, mode_strobe, bus_rw,clk, reset);
• inout [7:0] bus; // 'bus' is a bi-directional bus
• reg [7:0] bus_out; // 8 bit internal register for storing output values
• wire [7:0] bus_in; // this is used to get input data when 'bus' is acting as input.
• input data_strobe; // The Data Strobe signal on pin 14 of the parallel port.
• input mode_strobe; // The Mode Strobe signal on pin 17 (address strobe) // is used to indicate the setting of the mode in
fpga, Modes yet to be decided (TODO)
• input bus_rw; // Indicates the direction of data on the data_bus. Pin1 READ=1 WRITE = 0
• input reset; // No other special meanings. Negative edge resets, default high.
• input clk; // CLOCK!
• reg [7:0] row3 [33:0]; // 34 byte RAM
• reg [7:0] row2 [33:0]; // 34 byte RAM
• reg [7:0] row1 [33:0]; // 34 byte
• RAM reg [5:0] WAddr; // 6 bits to move upto 34th location
• reg [5:0] RAddr; // 6 bits to read 32 sobel outputs and future developments
• reg write_en,read_en; // internal registers for correct read/write operations.
• reg [5:0] index; // used as variable in shifting operation

Group -B 19
Contd…
• assign bus = (bus_rw)? bus_out : 8'dz; // this code enables the duplexing of 'bus'
• assign bus_in = (!bus_rw) ? bus : 8'dz; // -do-
• // codes till 'always' is for 32 sobels
• wire [7:0] out1;
• sobel s1(row1[0],row1[1],row1[2],
• row2[0],row2[2],
• row3[0],row3[1],row3[2],out1);
• wire [7:0] out2;
• .
• .
• .
• wire [7:0] out32;
• sobel s32(row1[31],row1[32],row1[33],
• row2[31],row2[32],
• Row3[31], row3[32],row3[33],out32);
• always @(posedge clk,negedge reset)
• begin
Group -B Major Project Final Presentation(2019), Department of
• if(!reset) 20
Contd…
• write_en <= 1'b1; // this ensures correct write operation
• end
• else if(!data_strobe & bus_rw & !read_en) // condition for reading from FPGA
• begin
• case (RAddr+1) // initially Rcode is written from 1.
• 1:bus_out <= out1; // this block will implement a 32:1 8 bit Vectored MUX
• 2: bus_out <= out2;
• 3: bus_out <= out3;
• .
• .
• 32: bus_out <= out32;
• default: bus_out <= 8'b0;
• endcase
• RAddr <= RAddr + 1; // incrementing to next RAddr location.
• read_en <= 1'b1; // to ensure correct read operation
• End
• else if(!mode_strobe & !bus_rw & !write_en) // condition for indicating FPGA the end of one row
• begin
• if(bus_in == 8'b0110_0110) // '66' is code indicating end of row
• Begin
• for(index=0;index < 34;index = index + 1) // this loop will implement row shift operation
• begin
• row1[index] <= row2[index];
• row2[index] <= row3[index];
• end

Group - B 21
Contd…
• WAddr <= 6'b0;
• RAddr <= 6'b0;
• write_en <= 1'b1; // to ensure shifting is done only once.
• end
• bus_out <= 8'b0;
• End
• else if(data_strobe & mode_strobe)
• begin
• write_en <= 1'b0;
• read_en <= 1'b0;
• end
• else
• Begin
• RAddr <= RAddr;
• WAddr <= WAddr;
• bus_out <= bus_out;
Group
• end- B 22
Results

Group-B 23
Block Diagram of Sobel Filter

Group - B 24
Conclusion
The Edge detection program is under processing. We converted
the image into raw data through MATLAB code and further
converted the raw data into text file in order to pass the argument
in Verilog code.

Group - 25
References
• [1] M.B. Ahmad and T.S.Choi ,” Local Threshold and Boolean Function Based Edge Detection,”IEEE Trans.
Consumer Electronics, vol.45, no.3,pp.674-679,1999.
• [2] J. Fan, D.K.Y. Yau , and A.K.Elmagarmid ,”Automatic Image Segmentation by integrating Color-Edge
Extraction and Seeded Region Growing ,” IEEE Trans. Image Processing,vol.10,no.10,pp.1454-1466,2001.
• [3] F. Russo and A. Lazzari ,” Color Edge Detection in Presence of Gaussian Noise Using Nonlinear
Prefiltering ,”IEEE Trans. Instrumentation and Measurement,vol.54,no.1,pp.352-358,2005.
• http://edge.kitiyo.com/2009/codes/sobel-edge-detection-verilog -code-full.html
• USC Computer Vision Bibliography

Group - 26

Area Optimized Fpga Implementation of Color Edge Detection: Project Guide - Dept of ETC Group - B

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Major Project Final Presentation (2019), Department of Electronics and Telecommunication Engg

AREA OPTIMIZED FPGA

Project Coordinator – Head of Department –

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

• textImage = zeros(row ,col , 3);

Major Project Final Presentation(2019), Department of

• textImage = zeros(row ,col , 3);

• for noI = 1:noImage

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

Major Project Final Presentation(2019), Department of

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