ANALOG LAYOUT DESIGN

(INDUSTRIAL TRAINING)
JASMEET KAUR
1511981509
B.E.(ECE)-2015
 PROJECT OVERVIEW
The project is about physical layout of
blocks using CAD tool. Simulations
like DRC (Design Rule Check), LVS
(Layout vs Schematic) and ERC
(Electrical Rule Check) to be
performed on the layout of the blocks.
WORK PLAN

During training period, prior knowledge of the operation and limits of the blocks that are used as elements of the
circuit was acquired. Followed by designing the physical layouts of blocks using CAD/ Magic tool. Also,
simulations like DRC, LVS, ERC to be performed on the layout of the blocks. Followed by SPICE simulations of the
circuits using netlist.

Installation &
understanding of
Analysing &
various SPICE
understanding Designing layouts Standard cell
simulation tools simulations of
the features and of cells using layouts and their
like ngSpice & various cells using
performance of CAD/Magic tools characterization
gschem netlists
basic cells.

1 2 3 4 5
 ANALYZING & UNDERSTANDING THE PROCESS OF
LAYOUT DESIGN
• Schematic fundamentals
1. The MOS transistor logic
2. Logic Gates
3. Transmission Gates
4. Review of fundamental electrical laws
• Layout Design
1. CMOS VLSI manufacturing process
2. Layers and connectivity
3. Process Design Rules
4. Verification (DRC, LVS)
 CONTINUED…
• Layout Design Flows
• Advanced Techniques for specialized building block layout design
1. Standard Cells
2. Special Logic Gates
3. Pad Cells
• Semiconductor Manufacturing Process
1. Semiconductors and pn junctions
2. MOS transistors
3. CMOS Processing
• Stick Diagrams as a tool for layouts
 DESIGNING LAYOUTS OF CELLS USING CAD/MAGIC
TOOLS

1. Inverter
2. NAND
3. AND
4. XNOR
5. 2:1 MUX
6. D Flip Flop
INSTALLATION & UNDERSTANDING OF VARIOUS SIMULATION
TOOLS LIKE NGSPICE & GSCHEM

• Basic understanding of ngSpice, gschem, eSim tools.

• Generating Netlists for cells.
1. Understanding of commands and syntax for generating the Netlists.
 SPICE SIMULATIONS OF VARIOUS CELLS USING NETLISTS
• Measuring delays in Analog world.
1. Propagation delay measurement
2. Transition delay measurement
• Setup and hold measurement & Metastability
• Impact of PVT variation
• Negative temperature bias, VT and delay relation changing, Temperature inversion
STANDARD CELL LAYOUTS AND THEIR CHARACTERIZATION
• Layout constraints like no rotation of cells
• Avoid metal-poly-metal connections
• Abutment should not violate the DRC
• PRboundary
• Working with Fixed Pitch, Pins being on the grid
Thank You!