Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Advance Electronics
References Material
a. “Microelectronic Circuits” MOSFET chapter, by Sedra and Smith
b. “CMOS Analog Circuit Design” , by Douglas R. Holberg and Phillip
E. Allen
Change of 1%
Complementary-Symmetry Metal–Oxide–Semiconductor
(or COS-MOS)
Complementary metal–oxide–semiconductor
(abbreviated as CMOS)
28
In today’s IC industry, a solid understanding of semiconductor devices
is essential—
more so in analog design than in digital design, because in the former,
transistors are not considered to be simple switches,
and many of their second-order effects directly impact the
performance.
Furthermore, as each new generation of IC technologies scales the
devices, these effects become more significant.
Since the designer must often decide which effects can be neglected
in a given circuit,
insight into device operation proves invaluable.
The ultimate goal is still to develop a circuit model for each device by
formulating its operation,
but this is accomplished through a good understanding of the
underlying principles.
29
2.1 General Considerations
MOSFET as a Switch
We must answer several questions.
For what value of VG does the device turn on?
In other words, what is the “threshold” voltage?
What is the resistance between S and D when the device is on (or
off)?
How does this resistance depend on the terminal voltages?
Can we always model the path between S and D by a simple linear
resistor?
What limits the speed of the device?
While all of these questions arise at the circuit level, they can be
answered only by analyzing the structure and physics of the
transistor.
30
Figure 4.1(b) cross-section. Typically L = 0.1 to 3 μm, W = 0.2 to 100 μ m, and the
thickness of the oxide layer (tox) is in the range of 2 to 50 nm.
Chap04-Sedra Smith 31
MOS Field-Effect Transistors (MOSFETs)
Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3
mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.
Chap04-Sedra Smith 32
MOSFET Structure
Leff and the gate oxide thickness, tox , play an important role in the
performance of MOS circuits.
Consequently, the principal thrust in MOS technology development is
to reduce both of these dimensions from one generation to the next
without degrading other parameters of the device.
Typical values at the time of this writing are Leff ≈10 nm and tox ≈15Å.
33
General Considerations
If the MOS structure is symmetric, why do we call one n region the
source and the other the drain?
In reality, the substrate potential greatly influences the device
characteristics.
That is, the MOSFET is a four-terminal device.
Since in typical MOS operation, the S/D junction diodes must be
reverse-biased, we assume that the substrate of NMOS transistors is
connected to the most negative supply in the system.
If a circuit operates between zero and 1.2 volts, Vsub,NMOS=0.
The actual connection is usually provided through an ohmic p+ region,
as depicted in the side view of the device.
34
In complementary MOS(CMOS) technologies, both NMOS and PMOS
transistors are available.
In practice, NMOS and PMOS devices must be fabricated on the same
wafer.
For the sake of brevity, we sometimes call NMOS and PMOS devices
“NFETs” and “PFETs,” respectively.
35
36
37
Vt = 0.5 to 1.0V
Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined
by vGS. Specifically, the channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS – Vt) vDS. Note that the
depletion region is not shown (for simplicity).
Chap04-Sedra Smith 38
Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by vGS.
Specifically, the channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS – Vt) vDS. Note that the depletion region is not
shown (for simplicity).
Chap04-Sedra Smith 39
MOS I/V Characteristics Threshold Voltage
41
In practice, the “native” threshold value obtained from the VTH
equation may not be suited to circuit design, e.g., VTH = 0 and the
device does not turn off for VG ≥ 0.
For this reason, the threshold voltage is typically adjusted by
implantation of dopants into the channel area during device
fabrication, in essence altering the doping level of the substrate near
the oxide interface.
For example, as shown in Fig. 2.7, if a thin sheet of p+ is created, the
gate voltage required to deplete this region increases.
43
Derivation of I/V Characteristics
If the mobile charge density along the direction of
current is Qd coulombs per meter and the velocity
of the charge is v meters per second, then
To understand why, we
measure the total charge
that passes through a cross
section of the bar in unit
time.
With a velocity v, all of the charge enclosed in v meters of the bar
must flow through the cross section in one second
44
A uniform channel
charge density
(charge per unit
length along the
source-drain path)
equal to
45
For semiconductors, v =μE, where μ is the mobility of charge carriers
and E is the electric field. Noting that E(x)=−dV/dx and representing
the mobility of electrons by μn, we have
L is the effective
channel length
Since ID is constant along the channel
Chap04-Sedra Smith 46
47
Dependence of ID upon
constants ……. ?
48
0.00007
I-V
VGS = 1
0.00006 0.5
VTH =
0.00005
0.00004
I 0.00003
0.00002
0.00001
0
0 0.25 0.5 0.75 1
VDS
50
Figure 4.4 The iD–vDS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, vDS, is kept small.
The device operates as a linear resistor whose value is controlled by vGS.
Chap04-Sedra Smith 51
For the arrangement in Fig. 2.14(a), plot the on-resistance of M1 as a
function of VG. Assume that μnCox = 50 μA/V2,W/L = 10, and
VTH=0.3V. Note that the drain terminal is open.
Since the drain terminal is open, ID = 0 and VDS = 0. Thus, if the device
is on, it operates in the deep triode region. For VG < 1 V + VTH, M1 is
off and Ron =∞. For VG > 1 V + VTH, we have
Chap04-Sedra Smith 52
1800.00
1600.00
1400.00
1200.00
1000.00
VG vs Ron
800.00
600.00
400.00
200.00
0.00
0.00 5.00 10.00 15.00 20.00
CMOS IC by Razavi Ch02 53
What happens if the drain-source
voltage exceeds VGS − VTH ?
ID does not follow the parabolic
behavior for VDS > VGS − VTH
54
Local density of the inversion-
layer charge is proportional to
VGS − V(x) − VTH
Thus, if V(x) approaches
VGS − VTH then Qd (x) drops
to zero.
If VDS is slightly greater than VGS − VTH,
then the inversion layer stops at x ≤ L
How does the device conduct current
in the presence of pinch-off?
55
As the electrons approach the pinch-off point (where Qd → 0), their
velocity rises tremendously (v = I /Qd ).
Upon passing the pinch-off point, the electrons simply shoot through
the depletion region near the drain junction and arrive at the drain
terminal.
56
The integral on the left-hand side of (2.7) must be taken from x = 0 to
x = L’, where L’ is the point at which Qd drops to zero, and that on the
right from V(x) = 0 to V(x) = VGS − VTH. As a result,
57
For PMOS devices
Chap04-Sedra Smith 58
On a VDS-VGS plane, show the
regions of operation of an NMOS
transistor.
Since the value of VDS with respect to VGS − VTH determines the region
of operation, we draw the line VDS = VGS − VTH in the plane, as shown
in Fig. 2.18. If VDS > VGS − VTH then the region above
the line corresponds to saturation
59
Chap04-Sedra Smith 60
VDS = VGS − VTH
VDS = VGS − VTH
VD - VS = VG - VS − VTH
VD = VG − VTH
VTH = VG − VD
VD > VG − VTH
VTH > VG − VD
pinch-off occurs
Chap04-Sedra Smith 61
Define a figure of merit that indicates how well a device converts
a voltage to a current
Chap04-Sedra Smith 62
63
For a PFET, the transconductance in the saturation region is
expressed as
Chap04-Sedra Smith 64
For the arrangement shown in Fig. 2.21, plot the transconductance as a
function of VDS.
65