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SUBJECT

Advance Electronics

CMOS IC by Razavi Ch01 1


Textbook
“Design of Analog CMOS Integrated Circuits” 2nd Edition 2017, by
Behzad Razavi (Chapters 1 to 6 and 9,10 & 12)

References Material
a. “Microelectronic Circuits” MOSFET chapter, by Sedra and Smith
b. “CMOS Analog Circuit Design” , by Douglas R. Holberg and Phillip
E. Allen

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ASSESMENT:
a. Project 5% (Individual level)
b. Assignments 10% (Tentatively every week)
c. Quizzes 15% (Tentatively every week)
d. OHTs Exam 30% (Two)
e. Final Exam 40% (One)
Note:
All assignments should be hand written, without any similarity with
your class fellows.

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Would this scenario send analog and RF designers to the
unemployment office?
An ADC that could digitize the minuscule RF signal
Only analog designers would be able to develop the ADC
A height of a few millivolts and a duration
of a few hundred microseconds

The sensing, processing, and transmission electronics in this


environment must consume a low amount of power
a. Use of a small battery for days or weeks, and
b. to minimize chip’s temperature, which could otherwise
damage the patient’s tissue.
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Multi-Level from Grouped Binary

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Unfortunately, the cable exhibits a finite bandwidth, attenuating high
frequencies and distorting the data as it reaches Laptop 2.
This device must now perform sensing and processing, the former
requiring an analog circuit (called an “equalizer”) that corrects the
distortion.
For example, since the cable attenuates high frequencies, we may
design the equalizer to amplify such frequencies, as shown
conceptually by the 1/|H| plot
Number of analog papers published at the International Solid-State
Circuits Conference (ISSCC) in recent years.
Air Bag

Change of 1%

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Analog Design Challenges
Transistor Imperfections As a result of scaling, MOS transistors continue
to become faster, but at the cost of their “analog” properties.
Declining Supply Voltages As a result of device scaling, the supply
voltage of CMOS circuits has inevitably fallen from about 12 V in the
1970s to about 0.9 V today.
Power Consumption The semiconductor industry, more than ever, is
striving for low-power design.
Circuit Complexity Today’s analog circuits may contain tens of
thousands of transistors, demanding long and tedious simulations.
PVT Variations Many device and circuit parameters vary with the
fabrication process, supply voltage, and ambient temperature. Robust
analog design in CMOS technology is a challenging task because device
parameters vary significantly across PVT.

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Assignment 01 ----- 18 to 25 Sep 2019
Tabulate the advantages and disadvantages of BJTs and MOSFETs in
general and compare their characteristics as given in Sedra and Smith.

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What is CMOS?

Complementary-Symmetry Metal–Oxide–Semiconductor
(or COS-MOS)
Complementary metal–oxide–semiconductor
(abbreviated as CMOS)

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NAND gate

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CMOS Inverter

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Simplified process of fabrication of a CMOS Inverter on p-type
substrate in semiconductor micro-fabrication.

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Basic MOS Device Physics
In studying the design of integrated circuits (ICs), one of two extreme
approaches can be taken,
(1) begin with quantum mechanics and understand solid-state
physics, semiconductor device physics, device modeling, and
finally the design of circuits; or
(2) treat each semiconductor device as a black box whose behavior is
described in terms of its terminal voltages and currents and
design circuits with little attention to the internal operation of the
device.
Experience shows that neither approach is optimum. In the first case,
the reader cannot see the relevance of all the physics to designing
circuits, and in the second, he or she is constantly mystified by the
contents of the black box.

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In today’s IC industry, a solid understanding of semiconductor devices
is essential—
more so in analog design than in digital design, because in the former,
transistors are not considered to be simple switches,
and many of their second-order effects directly impact the
performance.
Furthermore, as each new generation of IC technologies scales the
devices, these effects become more significant.
Since the designer must often decide which effects can be neglected
in a given circuit,
insight into device operation proves invaluable.
The ultimate goal is still to develop a circuit model for each device by
formulating its operation,
but this is accomplished through a good understanding of the
underlying principles.

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2.1 General Considerations
MOSFET as a Switch
We must answer several questions.
For what value of VG does the device turn on?
In other words, what is the “threshold” voltage?
What is the resistance between S and D when the device is on (or
off)?
How does this resistance depend on the terminal voltages?
Can we always model the path between S and D by a simple linear
resistor?
What limits the speed of the device?
While all of these questions arise at the circuit level, they can be
answered only by analyzing the structure and physics of the
transistor.

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Figure 4.1(b) cross-section. Typically L = 0.1 to 3 μm, W = 0.2 to 100 μ m, and the
thickness of the oxide layer (tox) is in the range of 2 to 50 nm.
Chap04-Sedra Smith 31
MOS Field-Effect Transistors (MOSFETs)

Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3
mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.

Chap04-Sedra Smith 32
MOSFET Structure

Leff and the gate oxide thickness, tox , play an important role in the
performance of MOS circuits.
Consequently, the principal thrust in MOS technology development is
to reduce both of these dimensions from one generation to the next
without degrading other parameters of the device.
Typical values at the time of this writing are Leff ≈10 nm and tox ≈15Å.

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General Considerations
If the MOS structure is symmetric, why do we call one n region the
source and the other the drain?
In reality, the substrate potential greatly influences the device
characteristics.
That is, the MOSFET is a four-terminal device.
Since in typical MOS operation, the S/D junction diodes must be
reverse-biased, we assume that the substrate of NMOS transistors is
connected to the most negative supply in the system.
If a circuit operates between zero and 1.2 volts, Vsub,NMOS=0.
The actual connection is usually provided through an ohmic p+ region,
as depicted in the side view of the device.

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In complementary MOS(CMOS) technologies, both NMOS and PMOS
transistors are available.
In practice, NMOS and PMOS devices must be fabricated on the same
wafer.
For the sake of brevity, we sometimes call NMOS and PMOS devices
“NFETs” and “PFETs,” respectively.

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Vt = 0.5 to 1.0V

Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined
by vGS. Specifically, the channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS – Vt) vDS. Note that the
depletion region is not shown (for simplicity).
Chap04-Sedra Smith 38
Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by vGS.
Specifically, the channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS – Vt) vDS. Note that the depletion region is not
shown (for simplicity).

Chap04-Sedra Smith 39
MOS I/V Characteristics Threshold Voltage

A “channel” of charge carriers is formed under the gate oxide


between S and D, and the transistor is “turned on. Interface is
“inverted”. The channel is also called the “inversion layer.” The value
of VG for which this occurs is called the “threshold voltage,” VTH. If VG
rises further, the charge in the depletion region remains relatively
constant while the channel charge density continues to increase,
providing a greater current from S to D.
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where φMS is the difference between the work functions of the
polysilicon gate and the silicon substrate, φF =(kT/q) ln(Nsub/ni ), k is
Boltzmann’s constant, q is the electron charge, Nsub is the doping
density of the substrate, ni is the density of electrons in undoped
silicon, Qdep is the charge in the depletion region, and Cox is the gate-
oxide capacitance per unit area. From pn junction theory,
Qdep = √4qεsi|φF|Nsub, where εsi denotes the dielectric constant of
silicon. Since Cox appears very frequently in device and circuit
calculations, it is helpful to remember that for tox ≈20Å,
Cox ≈17.25 fF/μm2. The value of Cox can then be scaled proportionally
for other oxide thicknesses.

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In practice, the “native” threshold value obtained from the VTH
equation may not be suited to circuit design, e.g., VTH = 0 and the
device does not turn off for VG ≥ 0.
For this reason, the threshold voltage is typically adjusted by
implantation of dopants into the channel area during device
fabrication, in essence altering the doping level of the substrate near
the oxide interface.
For example, as shown in Fig. 2.7, if a thin sheet of p+ is created, the
gate voltage required to deplete this region increases.

Called a “depletion-mode” FET, such a device was used in old


technologies. NFETs with a positive threshold are called
“enhancement-mode” devices.
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The turn-on phenomenon in a PMOS device is similar to that of
NFETs, but with all the polarities reversed. If the gate-source voltage
becomes sufficiently negative, an inversion layer consisting of holes is
formed at the oxide-silicon interface, providing a conduction path
between the source and the drain. That is, the threshold voltage of a
PMOS device is typically negative.

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Derivation of I/V Characteristics
If the mobile charge density along the direction of
current is Qd coulombs per meter and the velocity
of the charge is v meters per second, then
To understand why, we
measure the total charge
that passes through a cross
section of the bar in unit
time.
With a velocity v, all of the charge enclosed in v meters of the bar
must flow through the cross section in one second

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A uniform channel
charge density
(charge per unit
length along the
source-drain path)
equal to

V(x) is the channel


potential at x. VG − VD (near the drain)

charge carriers are negative

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For semiconductors, v =μE, where μ is the mobility of charge carriers
and E is the electric field. Noting that E(x)=−dV/dx and representing
the mobility of electrons by μn, we have

Subject to boundary conditions V(0)=0 and V(L)= VDS

L is the effective
channel length
Since ID is constant along the channel

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Dependence of ID upon
constants ……. ?

μnCox , the device


dimensions, W and L, and
the gate and drain potentials
with respect to the source

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0.00007
I-V
VGS = 1
0.00006 0.5
VTH =
0.00005

0.00004

I 0.00003

0.00002

0.00001

0
0 0.25 0.5 0.75 1
VDS

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The drain current is a
linear function of VDS

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Figure 4.4 The iD–vDS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, vDS, is kept small.
The device operates as a linear resistor whose value is controlled by vGS.

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For the arrangement in Fig. 2.14(a), plot the on-resistance of M1 as a
function of VG. Assume that μnCox = 50 μA/V2,W/L = 10, and
VTH=0.3V. Note that the drain terminal is open.
Since the drain terminal is open, ID = 0 and VDS = 0. Thus, if the device
is on, it operates in the deep triode region. For VG < 1 V + VTH, M1 is
off and Ron =∞. For VG > 1 V + VTH, we have

Chap04-Sedra Smith 52
1800.00

1600.00

1400.00

1200.00

1000.00
VG vs Ron
800.00

600.00

400.00

200.00

0.00
0.00 5.00 10.00 15.00 20.00
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What happens if the drain-source
voltage exceeds VGS − VTH ?
ID does not follow the parabolic
behavior for VDS > VGS − VTH

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Local density of the inversion-
layer charge is proportional to
VGS − V(x) − VTH
Thus, if V(x) approaches
VGS − VTH then Qd (x) drops
to zero.
If VDS is slightly greater than VGS − VTH,
then the inversion layer stops at x ≤ L
How does the device conduct current
in the presence of pinch-off?

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As the electrons approach the pinch-off point (where Qd → 0), their
velocity rises tremendously (v = I /Qd ).
Upon passing the pinch-off point, the electrons simply shoot through
the depletion region near the drain junction and arrive at the drain
terminal.

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The integral on the left-hand side of (2.7) must be taken from x = 0 to
x = L’, where L’ is the point at which Qd drops to zero, and that on the
right from V(x) = 0 to V(x) = VGS − VTH. As a result,

The drain-source voltage must be equal to


or greater than the overdrive voltage
VDS > VGS − VTH

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For PMOS devices

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On a VDS-VGS plane, show the
regions of operation of an NMOS
transistor.

Since the value of VDS with respect to VGS − VTH determines the region
of operation, we draw the line VDS = VGS − VTH in the plane, as shown
in Fig. 2.18. If VDS > VGS − VTH then the region above
the line corresponds to saturation

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Chap04-Sedra Smith 60
VDS = VGS − VTH
VDS = VGS − VTH
VD - VS = VG - VS − VTH
VD = VG − VTH
VTH = VG − VD
VD > VG − VTH
VTH > VG − VD
pinch-off occurs

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Define a figure of merit that indicates how well a device converts
a voltage to a current

We express gm in 1/Ω or in siemens (S)

Interestingly, gm in the saturation region is equal to the inverse of Ron


in the deep triode region.

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For a PFET, the transconductance in the saturation region is
expressed as

Chap04-Sedra Smith 64
For the arrangement shown in Fig. 2.21, plot the transconductance as a
function of VDS.

as VDS decreases from infinity

So long as VDS ≥ Vb − VTH, M1 is in saturation, ID is relatively


constant, and so is gm.

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