CMOS Switched Capacitor

Circuits
Contents

• Introduction
• Motivation
• Objectives
• Step Down Converters
• Step Up Converters
• Applications
• Conclusion
• References
Introduction
• Switched Capacitor Circuits are those that
comprises of only switches and capacitors as
their elements.
• If MOSFET’s are used as switches in these
circuits then these are called as CMOS
Switched Capacitor Circuits.
Motivation
• No Inductors which occupy larger area
• Minimal Electromagnetic radiation due to
absence of Inductors
• Simple Implementation
• High efficiency (> 80%)
• Low cost, Compact in Size
Objectives
• To get the desired voltage from the available
voltage applying them as input voltage to the
circuits which are should be designed
appropriately.
• To generate both from high to low(Step Down)
and low to high(Step Up) voltage conversions.
• A Circuit that step-down the voltage at the
output from its input is called as Step Down
converter, also known as Buck Converter.
• A Circuit that step-up the voltage at the
output from its input is called as Step Up
converter, also known as Boost Converter.
Some of the Step Down and Step Up Converters
are discussed below.
Step Down Converters
(Buck Converters)
Voltage Halver

Two phases : phi1 and phi2

Operation:

When phi1 is high

phi2 is low

When phi1 is low

phi2 is high
Charge expressions
Simulation Results
For RL=100k ohm , Vin = 1.8V

V ripple = 0.88077138V-0.8807176V
. = 0.053753622mV
For RL=1Mega ohm , Vin = 1.8V

V ripple = 0.89812207V-0.8981009V
. = 0.02118734mV
For RL=1Giga ohm , Vin = 1.8V

V ripple = 0.90017342V-0.9001569V
. = 0.016440533mV
Waveforms
For RL=1Giga ohm , Vin = 1.8V

V ripple = 1.6542533V-1.6533795V
. = 0.87384467mV
Multi Phase Switched Capacitor Step Down Converter
The maximum number of step-down conversion ratios possible are 2^n,
where n is the number of flying capacitors.

Equivalent circuit representation of Switched Capacitor Converter (SCC)

Step down SCC generates five conversion ratios(1/4, 1/3, 1/2, 2/3, 3/4)
using 2 flying capacitors
• The efficiency of the converter is determined by
two types of power losses: conduction and
switching.
• Conduction power losses are due to the power
dissipation in the MOSFET switches.
• Switching power losses are due to the charging
and discharging of parasitic capacitances.
• To calculate the conduction loss, we use the
model of figure (b).The Req in that figure, is the
equivalent series resistance of a SCC which can be
derived by the method presented in [1].
For a case of Conversion ratio 0.5
Equivalent Resistance vs Switching Frequency

= 901.1572mV-901.1456mV
. = 11.604389uV
Simulation Results
For RL=100k ohm , Vin = 1.8V , V(out)/Vin = 0.5

V ripple = 0.87733018V-0.8773192V
. = 0.01100873mV
For RL=1Mega ohm , Vin = 1.8V

V ripple = 0.89866761V-0.8986562V
. = 0.011434244uV
For RL=1Giga ohm , Vin = 1.8V

V ripple = 0.9011572V-0.9011456V
. = 0.011604389mV
Step Up Converters
(Boost Converters)
Voltage Doubler

Two phases : phi1 and phi2

Operation:

When phi1 is high

phi2 is low

When phi1 is low

phi2 is high
Charge expressions
Simulation Results
For RL=100k ohm , Vin = 0.9V

V ripple = 1.6542533V-1.6533795V
. = 0.87384467mV
For RL=1Mega ohm , Vin = 0.9V

V ripple = 1.7820633V-1.7819376V
. = 0.1256823mV
For RL=1Giga ohm , Vin = 0.9V

V ripple = 1.7981184V-1.7980837V
. = 0.034689903mV
Waveforms
For RL=1Giga ohm , Vin = 0.9V

. = 1.6542533V-1.6533795V
. = 0.87384467mV
Limitations
• A DC Signal of 1.8V is required to maintain the
substrate of PMOS at VDD.
• Clock signals of voltage level 1.8V is also
needed to drive the MOSFET’s as switches
present in the circuit.
Due to presence of these limitations for the
above technique various other Voltage
Doublers were proposed in order to step up
the low level (in 100’s of mV)voltages.
Charge pump cell
Waveforms
For Vin = 0.9V

. = 1.6542533V-1.6533795V
. = 0.87384467mV
DC output Charge Pump with PMOS bias
Simulation Results
For RL=100k ohm , Vin = 0.9V

V ripple = 1.5971099V-1.5961658V
. = 0.9441675mV
For RL=1Mega ohm , Vin = 0.9V

V ripple = 1.760121V-1.7596778V
. = 0.44314214mV
For RL=1Giga ohm , Vin = 0.9V

V ripple = 1.7773344V-1.7769531V
. = 0.38124676mV
Waveforms
For RL=1Giga ohm , Vin = 0.9V

= 1.6542533V-1.6533795V
. = 0.87384467mV
Voltage Doubler-1
Simulation Results
For RL=100k ohm , Vin = 0.9V

V ripple = 1.6733692V-1.6728547V
. = 0.51453033mV
For RL=1Mega ohm , Vin = 0.9V

V ripple = 1.7555622V-1.7551519V
. = 0.41023906mV
For RL=1Giga ohm , Vin = 0.9V

V ripple = 1.7642578V-1.7638423V
. = 0.41556054mV
Voltage Doubler-2
Simulation Results
For RL=100k ohm , Vin = 0.9V

V ripple = 1.6859034V-1.6853689V
. = 0.53409359mV
For RL=1Mega ohm , Vin = 0.9V

V ripple = 1.7685865V-1.7682108V
. = 0.37571036mV
For RL=1Giga ohm , Vin = 0.9V

V ripple = 1.7774771V-1.7770929V
. = 0.38416045mV
Waveforms
For RL=1Giga ohm , Vin = 0.9V

V ripple = 1.6542533V-1.6533795V
. = 0.87384467mV
Voltage Doubler-3

Block Diagram Implementation

Operation:
• When p1 clock is equal to +VDD (i.e. high) and p2 clock is 0
(i.e. low) MI is on, and node a1 is at approximately zero volts.
PMOS M4 is on so that node a2 is at VDD, bringing node b2 up
to approximately 2VDD since C2 was charged up to +VDD in
the previous half cycle. As a result, the NMOS M5, with the
gate tied to the node b2, is turned on, node b1 is at
approximately VDD, and the capacitor C1 is charged to +VDD
through M5 and M1. At the same time, since the node b2 is at
+2VDD and b1 is at +VDD, the PMOS M8 turns on and the
output is charged to +2VDD through M4 and M8, while the
device M7 is off.
• In the opposite phase, C2 is recharged to +VDD through M6
and M2, while the output is charged to 2vDD through M3, C1,
and M7.
Simulation Results
For RL=100k ohm , Vin = 0.9V

V ripple = 1.682287V-1.6821941V
. = 0.092847154mV
For RL=1Mega ohm , Vin = 0.9V

V ripple = 1.7821889V-1.7821795V
. = 0.0094241885mV
For RL=1Giga ohm , Vin = 0.9V

V ripple = 1.7921894V-1.7921846V
. = 0.0047683716mV
Waveforms
For RL=1Giga ohm , Vin = 0.9V

V ripple = 1.6542533V-1.6533795V
. = 0.87384467mV
Dickson Charge pump

Circuit Diagram
Simulation Results
For RL=100k ohm , Vin = 0.9V

V ripple = 0.91428014V-0.9138076V
. = 0.47252849mV
For RL=1Mega ohm , Vin = 0.9V

V ripple = 1.2335959V-1.2335309V
. = 0.065064884mV
Waveforms
For RL=1Giga ohm , Vin = 0.9V

V ripple = 1.7921894V-1.7921846V
.
Dickson_ncp1

Circuit Diagram
Operation:
• When phi1 is high V2 V2
phi2 is low
V4
MS2 will be ON since 2 > Vtn2

• When phi1 is low V1 V3

phi2 is high
V3
MS2 should be off but since the earlier condition is
satisfied MS2 is not in OFF condition which leads to
charging in reverse direction.
Simulation Results
For RL=100k ohm , Vin = 0.9V

V ripple = 2.1462448V-2.1451427V
. = 1.1020682mV
For RL=1Mega ohm , Vin = 0.9V

V ripple = 2.3925395V-2.3924161V
. = 0.12340131mV
Waveforms
For RL=1Mega ohm , Vin = 0.9V

V ripple = 2.3925395V-2.3924161V
. = 0.12340131mV
Dickson_ncp2

Circuit Diagram
Operation:
• When phi1 is high V2 V2
phi2 is low
V4

V2

MN2 will be OFF V2

MP2 will be ON
V4
MS2 will be ON
• When phi1 is low V1 V2
phi2 is high
V1

V3

MN2 will be ON V1
MP2 will be OFF
V3
MS2 will be OFF
Simulation Results
For RL=100k ohm , Vin = 0.9V

V ripple = 1.9324575V-1.9314588V
. = 0.99864682mV
For RL=1Mega ohm , Vin = 0.9V

V ripple = 2.4550163V-2.4548857V
. = 0.13058024mV
For RL=1Giga ohm , Vin = 0.9V

Output Voltage ~ 3V
Waveforms
For RL=1Giga ohm , Vin = 0.9V

V ripple = 2.4550163V-2.4548857V
. = 0.13058024mV
Waveforms
For RL=1Giga ohm , Vin = 0.9V

V ripple = 2.4550163V-2.4548857V
. = 0.13058024mV
At the output Stage
High Voltage Clock Generator
Simulation Results
For Vin = 0.9V

V ripple = 2.4550163V-2.4548857V
. = 0.13058024mV
Waveforms
For Vin = 0.9V

V ripple = 2.4550163V-2.4548857V
. = 0.13058024mV
Dickson_ncp3

Applying High Voltage Clock signal to Capacitor C5

Simulation Results
For RL=100k ohm , Vin = 0.9V

V ripple = 2.6846334V-2.6832532V
. = 1.3802384mV
For RL=1Mega ohm , Vin = 0.9V

V ripple = 3.1130952V-3.1129339V
. = 0.16131005mV
For RL=1Giga ohm , Vin = 0.9V

Output Voltage ~ 3.35V

Waveforms
For RL=1Giga ohm , Vin = 0.9V

V ripple = 1.6542533V-1.6533795V
. = 0.87384467mV
For RL=1Giga ohm , Vin = 0.9V

V ripple = 1.6542533V-1.6533795V
. = 0.87384467mV
For RL=1Mega ohm , Vin = 1.8V

V ripple = 6.8115211V-6.8111682V
= 0.35286557mV
Waveforms
For RL=1Mega ohm , Vin = 1.8V

V ripple = 1.6542533V-1.6533795V
. = 0.87384467mV
Waveforms
For RL=1Mega ohm , Vin = 1.8V

V ripple = 1.6542533V-1.6533795V
. = 0.87384467mV
Applications
Flash Memory
• Flash Memory has been widely used in
portable electronic devices for a couple of
decades. In programming this kind of devices,
high voltages are required to write and erase
the flash memory cells.
• Charge Pump Circuits are used in flash
memory systems in order to generate high
operation voltages for programming flash
memory cells.
Power Management of IoT nodes
• Power management of IoT nodes represents a challenging
task, especially when the output of the energy harvester is
in the order of few hundreds of milli volts.
• In IoT nodes, power-autonomy is achieved by scavenging
energy from the ambient using transducers, such as
photovoltaic(PV)cells , thermo electric generators(TEG).
• Due to the heavy dependence of their output signal from
the operating conditions, these transducers are often
unsuitable to feed directly to the circuit where they are
applied.
• Therefore, they employ a power management integrated
circuit (PMIC) to maximize conversion efficiency.
Power Management of IoT nodes

Simplified block diagram of a charge pump(CP) based energy harvesting Power

Management Integrated Circuit(PMIC).
Power Management of IoT nodes
• The input voltage, VIN, provided by an external
transducer, feeds a DC-DC converter and a clock
generation block. The converter is then opportunely
managed to obtain a precisely stable output voltage or
to optimize power consumption in function of the
required load current.
• SC converters with a voltage gain higher than one are
usually referred to as voltage multipliers or charge
pumps.
• Presently their field of application includes energy-
autonomous systems, such as battery-less circuits,
biomedical implants and, more recently, IoT nodes.
Conclusion
References
[1] Kushnerov, Alexander. ”High-efficiency self-adjusting switched capacitor
DC-DC converter with binary resolution.” arXiv preprint arXiv:1003.4301
(2010).
[2] Favrat, Pierre, Philippe Deval, and Michel J. Declercq. ”A high-efficiency
CMOS voltage doubler.” Solid-State Circuits, IEEE Journal of 33.3 (1998):
410-416.
[3] “A DC–DC Charge Pump Design Based on Voltage Doublers’’ Janusz A.
Starzyk, Senior Member, IEEE, Ying-Wei Jan, and Fengjing Qiu.
[4] “Design and Implementation of low power Dickson Charge Pump in
0.18μm CMOS Process’’ Aniruddha C. Kailuke, Pankaj Agrawal, R. V.
Kshirsagar
[5] Mahesh Zanwar, Subhajit Sen, " Programmable-Output Multi-phase
Switched Capacitor Step-down and Step-up CMOS DC-DC Converter”
[6] “SWITCHED-CAPACITOR DC-DC CONVERTERS FOR LOW-POWER ON-CHIP
APPLICATIONS ” Dragan MaksimoviC and Sandeep Dhar Colorado Power
Electronics Center Department of Electrical and Computer Engineering
University of Colorado, Boulder.
References
[7] “MOS Charge Pumps for Low-Voltage Operation’’ Jieh-Tsorng Wu,
Member, IEEE, and Kuen-Long Chang
[8] “A Dynamic Analysis of the Dickson Charge Pump Circuit” Toru Tanzawa
and Tomoharu Tanaka
[9] “Switched Capacitor Voltage Converters” Walt Kester, Brian Erisman, Gurjit
Thandi
[10] “A Review of Charge Pump Topologies for the Power Management of IoT
Nodes” Andrea Ballo , Alfio Dario Grasso,Gaetano Palumbo
[11] “An Overview of Charge Pumping Circuits for Flash Memory Applications”
Oi-Ying Wong, Rei Wong , Wing-Shan Tarn, and Chi-Wah Kok
[12] https://www.wikipedia.org/