VCAS 2019

(Paper Id-21)

Design and Analysis of Low Power SRAM

Pawar Dhiraj Kumar, Ritesh Kumar Kushwaha, P. Karuppanan

Presented by:
Dr. P. Karuppanan

Department of Electronics and Communication Engineering

Motilal Nehru National Institute of Technology Allahabad, Prayagraj-211004
 Outline
• Introduction

• Literature Review

• Objective

• Conventional Circuits and Proposed design

• Simulation Results

• Conclusion

• References 2
 Introduction
• In order to build a high rate processor, the CPU needs SRAM
cache memories.

• Cache memory -> consume more leakage power.

• Stable and an energy efficient SRAM is Challenges to design.

• To calculate leakage power various parameter such as Sub-

threshold current, gate leakage current and junction leakage
current are taken into consideration [1-2].

• In the literature various methods have been discussed to

minimized the power dissipation of an SRAM.
3
 Literature Review
• Voltage scaling method [4] -> Leakage power can be reduced by
operating in standby mode at low supply voltage.

• The gated-VDD (gated-GND) technique and dual-threshold voltage

(dual-Vt) technique have been discussed in [5].

• Sharifkhani et.al.[6] presented a technique in which, during the write

operation, the write-access transistors are controlled by a more
abounded voltage supply

• PPN based 10T SRAM cell (PPN10T) [9] and Transmission based
8T (TG8T) [10] has been recently reported

• chang et.al.[11] has been proposed novel circuit which contains two
word-lines and two access transistors. 4
 Objective
• Analysis of PPN based 10T SRAM cell (PPN10T),
Transmission based 8T (TG8T), conventional 6T SRAM
(C6T).

• Design a novel 8T SRAM cell to tackle the problems faced by

SRAM cells.

5
 Conventional Circuit

• Drive strength of pull-down device

and access device are given in eqns.
Wd
d   (Vcell  Vth ,d ) 2 (Vds ,d ) 2 (1)
Ld
W
 a   d (VWL  Vth ,a ) 2 (Vds ,a ) 2 (2)
La

• Drive strength of pull-down device

should be higher than that of
access device i. e. d ? a
Fig. 1 6T-SRAM cell

6
 Proposed design

• This circuit contained two extra

transistors N5 and N6 which will
provide a discharging path for a read
current
• Moreover two-tail transistors are
connected.
• In this approach, a large row in the
array of memory is partitioned into
a number of smaller identical sub-
blocks, and one pair of nMOS tail
Fig. 2: Modified 8T-SRAM cell
transistors controls each of these
blocks.

7
 Results and Discussion

Fig 3: Static noise margin (SNM) of C6T, Fig 4: Static noise margin (SNM) of 8T at
PPN10T, TG8T at supply voltage of 0.7 V supply voltage of 0.7 V

8
Contd…

Fig 3: Write Static noise margin (WSNM) of Fig 4: Write Static noise margin (WSNM) of
C6T, PPN10T ,TG8T at supply voltage of 0.7 P8T at supply voltage of 0.7 V
V

9
 Contd…

Fig 3: Read Static noise margin (RSNM) of Fig 6: Read Static noise margin (RSNM)
C6T, PPN10T and TG8T at supply voltage of of P8T at supply voltage of 0.7 V
0.7 V

10
Contd..

Table 1 : IREAD/ILEAK Comparison

Conventional 6T PPN Based 10T SRAM Transmission gate based Proposed 8T SRAM
SRAM(C6T SRAM) cell(PPN10T SRAM) 8T SRAM(TG8T SRAM) ( 8T SRAM)

Vdd Iread Ileak Iread/ Iread Ileak Iread/ Iread Ileak Iread/ Iread Ileak Iread/
(V) (µA) (nA) Ileak (µA) (pA) Ileak (µA) (pA) Ileak (µA) (pA) Ileak
( ×103) ( ×103) ( ×103) (×103)

0.3 0.041 0.0128 3.2 0.0077 0.395 19 0.016 3.508 19 0.0071 0.3807 18.64

0.4 0.565 0.152 3.7 0.1054 0.577 182 0.169 4.356 38 0.082 0.563 145

0.5 4.132 0.239 17.28 0.797 0.797 1000 1.096 5.204 210 0.544 0.757 718

0.6 17.411 8.004 2.17 3.840 1.067 3598 5.210 6.056 860 2.7769 0.969 2865

0.7 42.814 373.02 0.11 13.226 1.401 9440 16.513 6.916 2387 9.059 1.2059 7512

0.8 86.958 0.0176 0.0049 32.297 1.815 17790 35.070 7.792 4500 21.062 1.4735 14293

11
Contd..

Table 2 : Comparison of four SRAM cells

Design Specification Conventional PPN Based 10T Transmission gate based Proposed 8T
6T SRAM cell 8T SRAM SRAM
SRAM (C6T (PPN10TSRAM) (TG8T SRAM) ( 8T SRAM)
SRAM)

Process technology 45nm 45nm 45nm 45nm

Hold SNM (@ 0.7V) 275 mV 296 mV 280 mV 145 mV
Read SNM(@ 0.7V) 105 mV 290 mV 106 mV 160 mV

Write SNM(@ 0.7V) 224 mV 168 mV 265 mV 252 mV

Write access delay( Twa) 0.380 ns 0.9775 ns 0.4511 ns 0.4955 ns
Read access delay (Tra) 0.5022 ns 1.0226 ns 1.440 ns 1.2857 ns
Hold power dissipation 78.82 nW 25.63 nW 78.82 nW 11.98 nW
(@ 0.7 V)

Dynamic power 2.669 µW 2.314 µW 1.766 µW 0.9024 µW

dissipation (@ 0.7 V)

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 Conclusion
• Proposed 8T SRAM cell with Existing SRAM analyzed for
different parameters like write access time (TWA), read access
time(TRA), hold static noise margin, read SNM, write SNM,
Iread/Ileak ratio, hold power dissipation.

• The projected cell gives better WSNM.

• Hold and dynamic power dissipation is lowest, Iread/Ileak ratio ^

• Moreover, due to the dynamic voltage scaling technique, the

proposed circuit gives the lowest but enough hold SNM among
four cells.

13
 References
1. Babayan-Mashhadi, Samaneh, and Reza Lotfi. "Analysis and design of a low-voltage low-power double-
tail comparator." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22.2 (2014): 343-
352.
2. Nikoozadeh, Amin, and Boris Murmann. "An analysis of latch comparator offset due to load capacitor
mismatch." IEEE Transactions on Circuits and Systems II: Express Briefs 53.12 (2006): 1398-1402.
3. Ay, Suat U. "A sub-1áVolt 10-bit supply boosted SAR ADC design in standard CMOS." Analog Integrated
Circuits and Signal Processing 66.2 (2011): 213-221.
4. Mesgarani, Ali, et al. "Supply boosting technique for designing very low-voltage mixed-signal circuits in
standard CMOS." 2010 53rd IEEE international midwest symposium on circuits and systems. IEEE, 2010.
5. Ay, Suat U. "A sub-1áVolt 10-bit supply boosted SAR ADC design in standard CMOS." Analog Integrated
Circuits and Signal Processing 66.2 (2011): 213-221.
6. Sharifkhani, Mohammad, and Manoj Sachdev. "Segmented virtual ground architecture for low-power
embedded SRAM." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2 (2007): 196-
205.
7. Kulkarni, Jaydeep P., and Kaushik Roy. "Ultralow-voltage process-variation-tolerant schmitt-trigger-based
SRAM design." IEEE Trans. VLSI Syst. 20.2 (2012): 319-332.
8. Ahmad, Sayeed, et al. "Single-ended Schmitt-trigger-based robust low-power SRAM cell." IEEE
Transactions on Very Large Scale Integration (VLSI) Systems 24.8 (2016): 2634-2642.
9. Sanvale, Prachi, et al. "An improved read-assist energy efficient single ended PPN based 10T SRAM cell
for wireless sensor network." Microelectronics Journal (2019): 104611.
10. Pal, Soumitra, and Aminul Islam. "Variation tolerant differential 8T SRAM cell for ultralow power
applications." IEEE transactions on computer-aided design of integrated circuits and systems 35.4 (2015):
549-558.
11. Lo, Cheng-Hung, and Shi-Yu Huang. "PPN based 10T SRAM cell for low-leakage and resilient 14
subthreshold operation." IEEE Journal of Solid-State Circuits 46.3 (2011): 695-704.
Thank You!