1-57

Design and Implementation of a

Sub-Wavelength
All-Optical Logic Gates
Presented by
Saif Hassan Abdulnabi
Supervised by
Assist. Prof. Dr. Mohammed N. Abbas
Contents 2-57
1. Introduction.
2. Objectives.
3. Applications of the Research.
4. Definition of Plasmonics.
5. Generation of Plasmonics.
6. Limitation of Electronics and Photonics (The problem).
7. The Solution.
8. Plasmonic Logic Gates (1st Proposed Design).
9. Plasmonic Combinational Logic Functions (2nd Proposed Design).
10. Contributions.
11. Comparison with Previous Works.
12. Conclusions.
13. Suggestions for Future Works.
Introduction 3-57

 The study of Plasmonic is a branch of

Optoelectronics/Nanophonics Engineering. It
studies how the electromagnetic (EM) field can be
confined over a dimension of the order or smaller
than the wavelength.

Plasmonics is a technology in
which confinement of light occur.
Objectives 4-57

 To propose, design, analyze, simulate and achieve a

nanoscale integrated all-optical NOT, OR, AND, NOR,
NAND, XOR, and XNOR logic gates in the same
structure, in the same resonance frequency operating at
1550 nm wavelength, and in the same transmission
threshold based on Nano-ring Insulator-Metal-Insulator
(IMI) plasmonic waveguides.
 To propose, design, analyze, simulate and achieve a
nanoscale integration all-optical combinational logic
functions such as half-adder, half-subtractor, comparator
one-bit, and full-adder in the same structure, in the same
resonance frequency, and in the same transmission
threshold based on Nano-ring Insulator-Metal-Insulator
(IMI) plasmonic waveguides.
Applications of the Research 5-57

 In future, the proposed works (plasmonic logic

gates and plasmonic combinational logic
functions) are considered:
 The fundamental building blocks in photonic
integrated circuits and all-optical signal processing
systems.
 Pave the way to achieve ultra-high-speed optical chip
circuits and all-optical computers.
 6-57
Definition of Plasmonics
 The term ‘Plasmonic’ is derived from (plasma
of electronic), but the term of ‘Plasmonics’ is
refer to (applications of plasmonic).
 It is a collective wave where billions of
electrons oscillates in synchronization at
optical frequencies.
 Plasmons can travel along nanoscale wires.
 They can transfer information with high bit
rate.
 7-57
Generation of Plasmons
 Plasmons are generated at the metal-dielectric
interface.
 The excitation of a plasmon requires the
interaction of an electron passing through a thin
metal.
 Surface plasmons (or more exactly surface
plasmon polaritons, SPPs) are electro-magnetic
excitations that propagate along the interface
between a metal and dielectric medium.
Generation of Plasmons 8-57

(a)
Conditions of Good 9-57

Plasmonic Metal

1. Re ε𝒎 < 0 ,
2. Im ε𝒎 ˂˂−Re ε𝒎
Limitations of Electronics 10-57
 Electronics plays an important role in communication.
 In laboratories though, photonics has started replacing
electronics where a high data transfer rate is required.
 Electronics deals with the flow of charge (Electrons),
thus when the frequency of an electronic pulse
increases the electronic device becomes hot and wires
become very loose.
Limitations of Electronics11-57

 Hence, the principle ‘ the higher frequency,

the higher data transfer rate’ can not apply
and huge amount of data cannot be
transferred.
 The second obstacle is when the size of
electronic wire reduces, it’s resistance
increases. This leads to time delay effect.
Limitations of Photonics 12-57

 In photonics, optical fiber are used.

 The size of the optical fiber is in the order of
hundreds of nanometers during to diffraction limit.
 Huge amount of data cannot be sent along with
miniaturization.
What is the solution?
The solution is the PLASMONIC.
 Plasmonics can act as the bridge between
photonics and electronics for communication.
Limitations of Electronics13-57
and Photonics
 14-57

Plasmonic Logic Gates

and
Plasmonic Combinational
Logic Functions
(Proposed Design and Results)
Plasmonics Logic Gates 15-57
and Its Functions
 All-optical devices based on plasmonic waveguides
and effect of surface plasmons (SPs) play a great roll
in integrated optical logic gate and its functions due to:
a. Ultrahigh speed information processing.
b. High capacity.
c. Low power consumption.
d. Security to electromagnetic interference.
e. Overcoming the diffraction limit of light by surface
plasmon polaritons (SPPs).
f. Nanoscale size.
 Structure Layout for both
16-57
Objectives

Fig. 3(a) The proposed structure for the Fig. 3(b) The proposed structure for the proposed
proposed plasmonic seven logic gates plasmonic four combinational logic functions

• DIMENSIONS: Length=400 nm, Width= 400 nm, Width of stripes = 20nm,

Length of stripes = 400nm for the middle stripe and 250 nm for side stripes,
Nano-rings radii = 25nm and 50 nm respectively. Distance between stripes and
Nano-rings = 7.5nm. Width of PEC material = 50 nm.
Objectives Achievement 17-57

 The function of each proposed plasmonic logic gate

and each combinational logic function is achieved by
two factors:
1. The right choice for assigning the ports in the
structure (such as the input port(s), control port(s), and
output port(s)).
2. The right choice of the phase angle which makes the
constructive and destructive interferences between input
signal(s) and control signal(s).
Performance Measures 18-57

 The performance of the proposed plasmonic seven logic

gates and the proposed plasmonic four combinational logic
functions is measured by two criteria:

 T = Pout ⁄ Pin …(1)

 CR (dB)= 10 log((Pout|ON)min./(Pout|OFF)max.) …(2)

The Proposed Structure for Plasmonic NOT
Logic Gate 19-57

Fig. 4 The assigned ports for the proposed plasmonic NOT logic gate
Plasmonic NOT Logic Gate Performance 20-57

Table 1. Truth table of NOT gate

Transmission Contrast Ratio = 14 dB

Fig. 5 The transmission spectrum of the proposed plasmonic NOT logic gate for different
states, according to its truth table
The Proposed Structure for Plasmonic OR
21-57
and XOR Logic Gates

Fig. 6 The assigned ports for the proposed plasmonic OR and XOR logic gates
Plasmonic OR Logic Gate Performance 22-57

Table 2. Truth table of OR gate

Contrast Ratio = 9.5 dB

Transmission

Fig. 7 The transmission spectrum of the proposed plasmonic OR logic gate for different
states, according to its truth table
 Plasmonic XOR Logic Gate Performance 23-57

Table 3. Truth table of XOR gate

Contrast Ratio = 9.5 dB

Fig. 8 The transmission spectrum of the proposed plasmonic XOR logic gate for different
states, according to its truth table
The Proposed Structure for Plasmonic AND Logic 24-57
Gate

Fig. 9 The assigned ports for the proposed plasmonic AND logic gate
Plasmonic AND Logic Gate Performance 25-57

Table 4. Truth table of AND gate

Contrast Ratio = 10.13 dB

Fig. 10 The transmission spectrum of the proposed plasmonic AND logic

gate for different states, according to its truth table
The Proposed Structure for Plasmonic NOR 26-57
NAND, and XNOR Logic Gates

Fig. 11 The assigned ports for the proposed plasmonic NOR, NAND, and XNOR logic gates
 Plasmonic NOR Logic Gate Performance 27-57

Table 5. Truth table of NOR gate

Contrast Ratio = 6 dB

Fig. 12 The transmission spectrum of the proposed plasmonic NOR logic

gate for different t states, according to its truth table
Plasmonic NAND Logic Gate Performance 28-57

Table 6. Truth table of NAND gate

Contrast Ratio = 8 dB

Fig. 13 The transmission spectrum of the proposed plasmonic NAND logic

gate for different states, according to its truth table
Plasmonic XNOR Logic Gate Performance 29-57

Table 7. Truth table of XNOR gate

Contrast Ratio = 6 dB

Fig. 14 The transmission spectrum of the proposed plasmonic XNOR logic

gate for different states, according to its truth table
The Proposed Structure for Plasmonic Half-
Adder Combinational Logic Function 30-57

Fig. 15 The assigned ports for the proposed plasmonic half-adder combinational logic
function
Plasmonic Half-Adder Performance 31-57

Table 8. Truth table of Half-Adder

logic function

Contrast Ratio = 9.5 dB

Contrast Ratio = 10.13 dB

Fig. 16 The trans mission spectrum of the proposed plasmonic half-adder

combinational logic function for different states, according to its truth table
The Proposed Structure for Plasmonic Half-
Subtractor Combinational Logic Function 32-57

Fig. 17 The assigned ports for the proposed plasmonic half-subtractor combinational logic
function
Plasmonic Half-Subtractor Performance 33-57

Table 9. Truth table of Half-Subtarctor

logic function

Contrast Ratio = 9.5 dB

Contrast Ratio = 5.44 dB

Fig. 18 The transmission spectrum of the proposed plasmonic half-subtractor

combinational logic function for different states, according to its truth table
The Proposed Structure for Plasmonic
Comparator Combinational Logic Function 34-57

Fig. 19 The assigned ports for the proposed plasmonic comparator one-bit combinational
logic function
Plasmonic Comparator Performance 35-57

Table 10. Truth table of Comparator

One-bit logic function

Contrast Ratio = 6 dB
Contrast Ratio = 9.5 dB

Fig. 20 The transmission spectrum of the proposed plasmonic comparator

combinational logic function for different states, according to its truth table
The Proposed Structure for Plasmonic Full-
Adder Combinational Logic Function 36-57

Fig. 21 The assigned ports for the proposed plasmonic full-adder combinational logic
function
Plasmonic Full-Adder Performance 37-57

Contrast Ratio = 6 dB
Table 11. Truth table of Full-Adder
logic function
Contrast Ratio = 9.5 dB

Fig. 22 The transmission spectrum of the proposed plasmonic full-adder

combinational logic function for different states, according to its truth table
Contributions 38-57

 The proposed structure based on Plasmonic technique

to overcome the diffraction limit results in a Nano-
scale structure and a miniaturized photonic integrated
circuit.
 The proposed plasmonic logic gates structure is the
smallest structure in size compared with previous
related works.
 The proposed plasmonic combinational logic functions
structure is the smallest structure in size compared
with previous related works.
Contributions(Continued) 39-57
 Proposed, designed, analyzed, simulated, and achieved
largest number of plasmonic logic gates and plasmonic
combinational logic functions (seven logic gates and
four combinational logic functions) in the same
structure, in the same resonance wavelength, and in
the same transmission threshold.
 According to the knowledge of the researcher, so far,
there is no theoretical or experimental demonstration
of logic gates or combinational logic functions
structure that satisfies the requirements of ultra-small
feature size, seven plasmonic logic gates in one
structure, and four plasmonic combinational logic
functions in one structure.
Contributions(Continued) 40-57
 The transmission was enhanced (exceeding 100% in
some states for some proposed plasmonic logic gates
and in some proposed plasmonic combinational logic
functions.
 IMI technique is used in the proposed structures to
ensure getting the following properties (High
propagation length, Low propagation loss, Low
coupling loss, High quality factor, and High figure of
merit).
Contributions(Continued) 41-57
 For the first time according to the knowledge of the
researcher, so far, the proposed plasmonic logic gates
were designed and excited at 1550 nm wavelength,
making possible compatibility between the proposed
structure and optical communications systems in
future.
 The plasmonic full-adder combinational logic function
is achieved without the needing for their internal logic
gates.
Contributions(Continued) 42-57
 This work issued two general structures; the first
proposed plasomnic logic gates structure is regarded
as a general structure for performing any function for
logic circuits, which have one-input/one output and
two-inputs/one-output at 0.25 transmission threshold
in addition to perform the proposed seven plasmonic
logic gates.
Contributions(Continued) 43-57
 While the second proposed plasomnic combinational
logic function structure is regarded as a general
structure for performing any function for logic circuits
which have one-input/one-output, one-input/two-
outputs, two-inputs/one-output, and two-inputs/two-
outputs at 0.25 transmission threshold in addition to
perform the proposed seven plasmonic logic gates and
the proposed four plasmonic combinational logic
functions.
Comparison 1 44-57
Criteria This Work Paper 2012 Paper 2013 Paper 2015 Paper 2017 Paper 2019

Lumerical Finite Lumerical Finite Lumerical Finite Lumerical Finite Lumerical Finite
COMSOL
Difference Time Difference Time Difference Time Difference Time Difference Time
Software Multiphysics 5.3-
Domain (FDTD)- Domain (FDTD)- Domain (FDTD)- Domain (FDTD)- Domain (FDTD)-
Program Used 2D
2D 2D 2D 2D 2D

Plasmonic Metal-
Square Micro-
Nano-ring Insulator-Metal Ring Resonator
MIM-Plasmonic Micro-ring Metal- ring Metal-
Insulator- Metal- (MIM) Nano- Metal-Insulator-
Proposed Waveguides with Insulator-Metal Insulator-Metal
Insulator (IMI) Waveguides with Metal (MIM)
Structure Nano-Disk (MIM) Plasmonic (MIM) Nonlinear
Plasmonic Nano- Slot Cavity Plasmonic
Resonator Waveguies Plasmonic
Waveguies Resonator Waveguides
Waveguies

Number of
Proposed Logic 7 Gates 4 Gates 1 Gate 3 Gates 3 Gates 2 Gates
Gates

NOT, OR, AND,

Proposed Logic NOT, NAND, NOT, AND, and NOT, OR, and
NOR, NAND, NOT AND and NOR
Gates XOR, and XNOR NOR XOR
XOR, and XNOR

Realization of All proposed The proposed The proposed The proposed The proposed The proposed
Proposed Plasmonic logic plasmonic logic plasmonic logic plasmonic logic plasmonic logic plasmonic logic
plasmonic Logic gates are realized gates are realized gate is realized in gates are realized gates are realized gates are realized in
Gates in one structure in two structures one structure in two structures in one structure one structure
Comparison 1 (Continued) 45-57
750 nm ×
400 nm × 400 1220 nm × 1120 900 nm 760 nm × 600 More than
Size 2.4 𝜇m × 3 𝜇m
nm nm and nm 3 𝜇m × 2 𝜇m
1.5 𝜇m × 1.8 𝜇m

Operating
1550 nm 525 nm 850 nm 1535 nm 1535 nm
Wavelength(s) 944 nm and 999 nm

Dielectric
Teflon Air Air SiO2 Air Air
Material Used

Nobel Metal Used Silver Silver Silver Silver Silver Silver

Model of
Description the
Johnson and
Relative Drude Model Drude Model Drude Model Drude Model Drude Model
Christy Data
Permittivity of
the Silver

Performance Transmission and Transmission and Transmission and Transmission and

Transmission Transmission
Measured Contrast Ratio Contrast Ratio Contrast Ratio Contrast Ratio

Transmission
Threshold 0.2 or 20% 0.5 or 50%
0.25 or 25% 0.30 or 30% 0.3 or 30% 0.5 or 50% or Less
between ON/OFF or Less or Less
States
Contribution 1 (Continued) 46-57

112.3% at NOT
Gate

175% at OR
Gate

72% at AND
25% at NAND 70% at NOT 38% at NOT
Gate
Gate Gate Gate
84.06% at AND
28.07% at Gate
Maximum 42% at XOR 65.35% at NOT 70% at NOR 80% at OR
NOR Gate
Transmission % Gate Gate Gate Gate
80.07 at NOR
112.3% at Gate
25% at XNOR 90% at AND 40% at XOR
NAND Gate
Gate Gate Gate
63% at XOR
Gate

175% at XNOR
Gate

Exists in NOT
Amplifying of Gate, OR Gate,
Does Not Exist Does Not Exist Does Not Exist Does Not Exist Does Not Exist
Transmission NAND Gate,
and XNOR Gate
Comparison 2 47-57
Criteria This Work Conference 2015 Paper 2015 Paper 2016 Paper 2017 Paper 2017

Lumerical Finite Lumerical Finite Lumerical Finite

COMSOL COMSOL COMSOL
Difference Time Difference Time Difference Time
Software Multiphysics 5.3- Multiphysics 5.3- Multiphysics 5.3-
Domain (FDTD)- Domain (FDTD)- Domain (FDTD)-
Program Used 2D 2D 2D
2D 2D 2D
Linear
Ring Resonator Mach–Zehnder
Nano-Rings Interference
Based Interferometer
Insulator- Metal- Effects in Nonlinear
Proposed Plasmonic Metal Metal–Insulator– (MZI)
Insulator (IMI) Dielectric Plasmonic
Structure Slot Waveguides Metal (MIM) Using a
Plasmonic Nano- Crossed Nanocavities
Plasmonic Plasmonic MIM
Waveguides Waveguide
Waveguides Waveguides
Structure
Number of
4 1 1 2 2 1
Proposed
Combinational Combinational Combinational Combinational Combinational Combinational
Combinational
Logic Functions Logic Functions Logic Functions Logic Functions Logic Functions Logic Functions
Logic Functions
Half-Adder, Half-
Proposed Subtractor,
Half-Adder, and Half-Adder and Comparator One-
Combinational Comparator One- Half-Adder Half-Adder
Half-Subtractor Full-Adder Bit
Logic Functions Bit,
and Full-Adder

More than Less than 15 𝜇m

850 nm × 400 10 𝜇m × 17 𝜇m ×
Size Not Available 1260 nm × ×
nm 28 𝜇m 3 𝜇m
1260 nm 15 𝜇m
Comparison 2 (Continued) 48-57

630 nm, 901 nm,

Operating 750 nm and 770
1550 nm 530 nm 800 nm 1775 nm, and 1550 nm
Wavelength(s) nm
1856 nm

Organically
Dielectric Non-Linear Kerr
Teflon SiO2 Modified Silica Air Air
Material Used Material
(ORMOSIL)

Nobel Metal Used Silver Gold Gold Silver Gold Silver

Model of
Description the
Johnson and Drude-Lorentz Drude-Lorentz
Relative Not Available Not Available Not Available
Christy Data Model Model
Permittivity of
the Metal

Performance Output Optical Transmission and

Intensity Transmission Intensity
Measured Transmission Power Contrast Ratio
Conclusions 49-57

 The principle operation of the proposed plasmonic logic gates

and the proposed plasmonic combinational logic functions is
based on the constructive and destructive interferences
between the input signal(s) and control signal(s).
 The constructive and destructive interferences can be achieved
by the same phase of the input (or control) signals and phase
difference between the input (or control) signals, respectively.
Conclusion (Continued) 50-57

 The proposed plasmonic logic gates and the proposed

plasmonic logic functions can be achieved by the right choice
for assigning the ports in the proposed structures (which is an
input port(s), which is a control port(s), and which is an output
port(s)), and the right choice of phase angle which makes the
constructive and destructive interferences between input
signal(s) and control signal(s).
 The proposed value of the transmission threshold which must
be depended in order to achieve all seven proposed plasmonic
logic gate in one structure and achieve all four proposed
plasmonic combinational logic functions in one structure is
0.25 (or 25%).
Conclusion (Continued) 51-57

 The transmission in the proposed works is minimized or

maximized depending on the size, shape, and parameters of
the proposed structure (except the side stripes length),
materials and refractive index of the chosen materials, the port
position, the polarization of incident field and its phase.
 According to the size, the shape, the parameters, and the
materials of structure, the SPP is excited at 1550 nm
wavelength.
Conclusion (Continued) 52-57

 The factors that affect the changing of the desired wavelength

(1550 nm), when the size and shape of the proposed structures
remain unchanged, are metal, dielectric (slightly linear
proportional with the desired wavelength), outer radius of the
Nano-ring (linear proportional with the desired wavelength),
side stripes length (linear proportional with the desired
wavelength with slope of 2), and stripes width. While the
factors, which have a small effect on the changing of the
desired wavelength under the same conditions are the inner
radius of the Nano-ring and coupling distance.
Suggestions for Future 53-57

Works
 Constructing the proposed plasmonic logic gates and the
proposed plasmonic logic circuits practically via the modern
fabrication technology and modern devices.
 Reducing the size and structure parameters as much as
possible, in accordance with its manufacturer and application
in fabrication techniques.
 Increasing the numbers and functions of the plasmonic
combinational logic circuits in one structure to produce all-
optical Arithmetic Logic Unit (ALU).
Suggestions for Future 54-57

Works (Continued)
 Reducing the losses due to the metal by choosing a metal
which has low losses such as graphene or using a gain
material to compensate the losses due to the metal used.
 Constructing plasmonic reversible logic gates such as Wire
gate, Not gate, Swap gate, Feynman gate, Toffoli gate, and
Fredkin gate.
 Constructing plasmonic reversible combinational logic
circuits.
Suggestions for Future 55-57

Works (Continued)
 Proposing a structure to perform the proposed plasmonic logic
gates or the proposed plasmonic combinational logic functions
with a high transmission threshold value up to a default
threshold value of 0.5 or 50%.
 Improving the contrast ratio as much as possible for
plasmonic logic gates and for plasmonic combinational logic
functions to improve their performance.
 Enhancing the transmission value as much as possible to be
more than 90% or exceeding 100% for all ON output states.
 Reducing the transmission value as much as possible for all
OFF output states.
Suggestions for Future 56-57

Works (Continued)
 Using hybrid plasmonic waveguide as a new technique used
recently in modern research.
 Proposing a general structure to perform more than two-
inputs/two-outputs plasmonic logic circuit.
 ‫‪57-57‬‬

‫من جعل الشكر خاتمة‬

‫النعم جعلها هللا فاتحة المزيد‬
‫واخر دعوانا ان الحمد هلل رب‬
‫العالمين‬
‫والصالة والسالم على نبينا‬
‫محمد (ص) وعلى اله الطيبين‬
‫الطاهرين‬