Internal JTAG(IJTAG)-IEEE STD.

1687

AMAN TYAGI
Outline
JTAG Boundary Scan , IEEE 1149.1 Standard
Why IJTAG ?
IEEE Std. 1687 Architecture
Comparison with 1149.1
Summary
Q & A
JTAG Boundary Scan , IEEE 1149.1 Standard

Schematic Diagram of a JTAG enabled device

(Source:https://www.corelis.com/education/tutorials/jtag-tutorial/jtag-technical-
primer/)
 JTAG Boundary Scan , IEEE 1149.1 Standard

(Source:https://www.intel.com/content/dam/www/programmable/us/en/
pdfs/literature/hb/stx3/stx3_siii51013.pdf)
JTAG Boundary Scan , IEEE 1149.1 Standard

TAP State machine

(Source :https://www.xjtag.com/about-jtag/jtag-a-technical-overview/
Why IJTAG ?
There is growing level of functionality within each silicon chip
or die.
Characterization, Debug and Testing of all IPs can be a
challenging task.
Require embedded instruments (~100s to 1000s).
Example of On chip Instruments : Test Registers ,
Configuration Registers, Monitors, Different Power Mode,
Clock Controls etc.
The number of on chip instruments is increasing and
accessing instruments through JTAG demand a streamlined
procedure or standard.
Why IJTAG ?
IJTAG (IEEE STD. 1687 STANDARD) IS A WAY OUT!

Handles the heterogeneous set of embedded instruments

(test features, monitors, IPs, test logic, embedded blocks) .
Standardizes the instrument interface .
Provides a mechanism on how these instruments are
connected .
Connects to Standard JTAG/TAP 1149.1 .
A language to create read/write/scan tasks for each
instruments .
Why IJTAG ?
IJTAG ENABLES EASY INTEGRATION!

Source: http://www.semiwiki.com/forum/content/2447-better-ip-test-ieee-p1687.html
IEEE Std. 1687 Architecture
1687 provides the
standardization of
this interface

Source: IJTAG Standards, IEEE

IEEE Std. 1687 Architecture
Segment Insertion Bit
A SIB is a single TDR bit that can be
placed anywhere in the P1687
architecture.
Allows to flexibility to include an
instrument in a network or exclude.

Source :IEEE P1687 Internal JTAG (IJTAG) taps into embedded instrumentation By Al Crouch
IEEE Std. 1687 Architecture
Instrument Connectivity Language
ICL essentially describes where the IJTAG TDRs are.
 The scan paths that connect and access them, how and when these scan paths should vary,
the connections between the IJTAG scan paths and the boundary-scan TAP controller on the
device,
and the parallel connections between the embedded IJTAG instruments and the IJTAG TDRs.
Basically , it describes the network which include Components , Connectivity and Interface.
IEEE Std. 1687 Architecture
Procedural Description Language
 PDL represents the test vectors or operational procedures that are applied directly to
instruments .
Contains basic iReads and iWrites (that is, IJTAG reads and writes)
Other PDL features :flow-control operatives such as if-then-else, for-next, do-while and others
Enables us to control and automate the operation and scheduling of embedded instruments
independently of any IJTAG access network they may be connected to.
Basically , it describes instrument’s access ,behavior and scope
IEEE Std. 1687 Architecture

Source :IEEE P1687 Internal JTAG (IJTAG) taps into embedded instrumentation By Al Crouch
Comparison with IEEE 1149.1
Parameter
External interface to internal
elements.
Internal control
Instrument access
Register Size
Test Vector reuse
JTAG IJTAG
Instrumentation control is vendor Standardised and with plug-and-
specific. play capability.
Ad-hoc and typically vendor Standard protocol.
specific.
manually defined at the JTAG TAP Automated re-targeting from
interface. IJTAG TAP to instrument through
a logical hierarchical structure.
Fixed for each instruction Variable
No Yes
 Summary
Describes a generic and flexible way of describing network of instruments
Interments to be used for test, debug, calibration, characterization and monitoring etc
Uses basic TDRs and SIBs components
ICL – Instrument Connectivity Language
Ability to describe the network components, interface and connectivity to other components
PDL – Procedural Description Language
Ability to describe the function (read/write) of an instrument at any level of the design.
Provides standard protocol to interface internal and external IPs
Enables Plug and Play approach for inserting and connecting
Thank You. QUESTIONS?