Sei sulla pagina 1di 61

MICROCONTROLLER

INSTRUCTION SET

10/5/2019
Introduction
 An instruction or a line of code is an order or command
given to a processor by a computer program. All commands
are known as instruction set and set of instructions is known
as program.
 8051 have in total 111 instructions, i.e. 111 different words
available for program writing.

10/5/2019
 Label: a label is a name or symbol given to the address number.

label: instruction ;comment(s)


An assembly Language instruction line

Example for label names:


transmit:
square:
receive:

10/5/2019
Instruction:
 Every instruction can be converted into unique Machine
language binary code .
 Each instruction is made up of three distinct part .

 Instruction Part 1 2 3
mov destination, source
(mnemonic) (operands)

10/5/2019
Instruction Format
 Where first part describes WHAT should be done, while
other explains HOW to do it.
 Part 2 is called operand or data address –It specifies the
destination for the data that is being copied from the source.
 Part 3-operand containing the address of the source location.
 Depending upon the number of bytes required to represent 1
instruction completely.

10/5/2019
Types Of Instructions
 Instructions are divided into 3 types;

1. One/single byte instruction.

2. Two/double byte instruction.

3. Three/triple byte instruction.

10/5/2019
Types Of Instructions
1. One/single byte instructions :

 If operand is not given in the instruction or there is no


digits present with instruction- the instructions can be
completely represented in one byte opcode.

 OPCODE 8 bit

EX: NOP
CLR
RET

10/5/2019
Types Of Instructions
2. Two/double byte instruction:

 If 8 bit number is given as operand in the instruction, then


such instructions can be completed represented in two
bytes.

 First byte OPCODE


 Second byte 8 bit data or I/O port
Ex: MOV A,direct ;
 Move direct byte to Accumulator

10/5/2019
Types Of Instructions
3. Three/triple byte instruction:

 If 16 bit number is given as operand in the instructions


then such instructions can be completely represented in
three bytes 16 bit number specified may be data or address.

10/5/2019
Types Of Instructions
1. First byte will be instruction code.
2. Second byte will be 8 LSB’s of 16 bit number.
3. Third byte will be 8 MSB’s of 16 bit number.

 First byte OPCODE.


 Second byte 8 LSB’s of data/address.
 Third byte 8 MSB’S of data/address.

EX:
 LJMP addr16

10/5/2019
Addressing Modes
 Addressing modes specifies where the data (operand) is. They
specify the source or destination of data (operand) in several
different ways, depending upon the situation.

 Addressing modes are used to know where the operand


located is.

10/5/2019
Addressing Modes
 There are 5 types of addressing modes:

1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Register indirect addressing
Accessing
5. Index addressing. memories

10/5/2019
Immediate Addressing Mode
 In immediate addressing mode, the data is given with the
instruction itself.
 In this case; the data to be stored in memory immediately
follows the opcode.
 Can load information into any registers, including 16-bit
DPTR register
 DPTR can also be accessed as two 8-bit registers, the high byte DPH
and low byte DPL

10/5/2019
Immediate Addressing Mode
For example;
 MOV A, #25H (This instruction will move the data 25H to
accumulator---load 25H into A)
 MOV R4,#62 ;load 62 into R4
 MOV B,#40H ;load 40H into B
 MOV DPTR,#4521H ;DPTR=4512H
MOV DPL,#21H ;This is the same
MOV DPH,#45H ;as above

10/5/2019
Immediate Addressing Diagram

Instruction

Opcode Operand
Register Addressing Mode
 In register addressing mode; the source and/or destination is
a register.

 In this case; data is placed in any of the 8 registers(R0-R7); in


instructions it is specified with letter Rn (where N indicates
0 to 7).

10/5/2019
Register Addressing Diagram
Instruction

Opcode Register Address R


Registers

Operand
Register Addressing Mode
For example:
• ADD A, Rn (This is general instruction).
• ADD A, R5 (This instruction will add the contents of
register R5 with the accumulator contents).
Example
 MOV A,R0 ;copy contents of R0 into A
 MOV R2,A ;copy contents of A into R2
 ADD A,R7 ;add contents of R7 to A

10/5/2019
Direct Addressing Mode
 In direct addressing mode; the address of memory location
containing data to be read is specified in instruction.

 In this case, address of the data is given with the instruction


itself.

10/5/2019
Direct Addressing Diagram
Instruction

Opcode Address A
Memory

Operand
Direct Addressing Mode
 For example;

1. MOV A, 25H (This instruction will read/move the data


from internal RAM address 25H and store it in the
accumulator.

10/5/2019
Register Indirect Addressing Mode
 In register indirect addressing mode, the contents of the
designated register are used as a pointer to memory.

 In this case; data is placed in memory, but address of memory


location is not given directly with instruction.
 R0 and R1 are used as pointers for this instruction.

10/5/2019
Indirect Addressing Diagram
Instruction

Opcode Address A
Memory

Pointer to operand

Operand
Register Indirect Addressing Mode
 For example;

1. MOV A,@R0 This instruction moves the data from the


register whose address is in the R0 register into the
accumulator.

10/5/2019
Index Addressing Mode
 Offset (from accumulator) is added to the base index register
(DPTR OR Program Counter) to form the effective address
of the memory location.
 Indexed addressing mode is widely used in accessing data
elements of look-up table entries located in the program
ROM
 The instruction used for this purpose is MOVC ,@A+DPTR
 Use instruction MOVC, “C” means code
 The contents of A are added to the 16-bit register DPTR to
form the 16-bit address of the needed data

10/5/2019
Index Addressing Mode
 For example:

1. MOVC A, @ A + DPTR ( This instruction moves the data


from the memory to accumulator; whose address is
computed by adding the contents of accumulator and
DPTR)

10/5/2019
Types Of Instructions
1. Data transfer instructions.
2. Arithmetic instructions.
3. Logical instructions.
4. Logical instructions with bits.
5. Branch instructions.

10/5/2019
Data Transfer Instructions
 These instructions move the content of one register to
another one.

 Data can be transferred to stack with the help of PUSH and


POP instructions.

10/5/2019
Data Transfer Instructions
 MNEMONIC DESCRIPTION
 MOV A,Rn (A) (Rn)
 MOV A,R1 (A) (R1)
 MOV A,@Ri (A) (Ri)
 MOV A,#X (A) Data
 MOV Rn,A (Rn) (A)
 MOV Rn, Rx (Rn) (Rx)
 MOV Rn, #X (Rn) Data
 MOV Rx, A (Rx) (A)
 MOV Rx, Rn (Rx) (Rn)
10/5/2019
Data Transfer Instructions
 MOV Rx, Ry (RX) (Ry)
 MOV Rx, @ Ri (Rx) (Ri)
 MOV Rx, # X (Rx) Data
 MOV @ Ri, A (Ri) (A)
 MOV @ Ri, Rx (Ri) (Rx)
 MOV @ Ri, #X (Ri) Data
 MOV DPTR, #X (DPTR) Data
 MOVC A @ A+DPTR (A) (A+DPTR)
 MOVC A@ A+PC (A) (A+PC)

10/5/2019
Data Transfer Instructions

 MOVX A,@ Ri A (Ri)

 MOVX A, @ DPTR (A) (DPTR)

 MOVX @Ri, A (Ri) (A)

10/5/2019
Data Transfer Instructions
 MOVX @ DPTR, A (DPTR) (A)

 PUSH Rx Push directly addressed Rx register on stack

 POP Rx (A) (Rx)

10/5/2019
Data Transfer Instructions
 XCH A, Rn (A) (Rn)

 XCH A, Rx (A) (Rx)

 XCH A, @Ri (A) (Ri)


 XCHD Exchange 4 lower
bits in accumulator with
indirectly addressed register

10/5/2019
Arithmetic Instructions
 These instructions perform several basic operations. After
execution, the result is stored in the first operand.

 8 bit addition, subtraction, multiplication, increment-


decrement instructions can be performed.

10/5/2019
Arithmetic Instructions
 MNEMONICS DESCRIPTION

 ADD A, Rn A = A + Rn

 ADD A, direct A = A + direct

 AAD A, @ Ri Add indirect


RAM to A

10/5/2019
Arithmetic Instructions
 ADD A, # X Add immediate data to accumulator
 ADDC A, Rn A = A + Rn + C
 ADDC A , Rx A = A + Rx + C
 ADDC A, @ Ri A = A + Ri + C
 ADDC A, # X A = A + Byte + C
 SUBB A, Rn A = A – Rn – 1

10/5/2019
Arithmetic Instructions
 SUBB A, Rx A = A – Rx

 SUBB A, @ Ri A = A – Ri

 SUBB A, # X A = A – Byte

 INC A A =A + 1

 INC Rn Rn = Rn + 1

 INC Rx Rx = Rx + 1 10/5/2019
Arithmetic Instructions
 INC @ Ri Ri = Ri + 1

 DEC A A =A – 1

 DEC Rn Rn = Rn – 1

 DEC Rx Rx = Rx – 1

 DEC @ Ri Ri = Ri – 1

 INC DPTR DPTR = DPTR + 1 10/5/2019


Arithmetic Instructions
 MUL AB B:A = A * B

 DIV AB A = [A/B]

10/5/2019
Logical Instructions
 These instructions perform logical operations between two
register contents on bit by bit basis.

 After execution, the result is stored in the first operand.

10/5/2019
Logical Instructions
 MNEMONIC DESCRIPTION
 ANL A, Rn (A) (A) ^ (Rn)
 ANL A, Rx (A) (A) ^ (Rx)
 ANL A,@ Ri (A) (A) ^ (Ri)
 ANL A, # X (A) (8 bit data) ^ (A)
 ANL Rx, A (Rx) (A) ^ (Rx)
 ANL Rx,# X (Rx) (8 bit data) ^ (Rx)

10/5/2019
Logical Instructions

 ORL A, Rn (A) (A) + (Rn)

 ORL A, Rx (A) (A) + (Rx)

 ORL A, @ Ri (A) (A) + (Ri)

10/5/2019
Logical Instructions
 ORL Rx, A (Rx) (A) + (Rx)

 ORL Rx,# X (Rx) (8 bit data) + (Rx)

 XORL A, Rn Logical exclusive


OR operation between the contents of accumulator and R
register.

10/5/2019
Logical Instructions
 XORL A, Rx Logical exclusive OR
operation between the contents of the accumulator and
directly addressed register Rx.
 XORL A,@ Ri Logical exclusive OR
operation between the contents of the accumulator and
indirectly addressed register.
 XORL A, # X Logical exclusive OR
operation between the contents of accumulator and the
given 8 bit data.
 XORL Rx, A Logical exclusive OR
operation between the contents of the accumulator and
directly addressed register Rx. 10/5/2019
Logical Instructions
 XORL Rx, # X Logical exclusive OR
operation between the contents of the directly addressed
register Rx and the given 8 bit data.
 CLR A (A) 0
 CPL A (A) (A)
 SWAP A (A3-0) (A7-4)

10/5/2019
Logical Instructions
 RL A (An + 1) (An)
(A0) (A7)

 RLC A (An + 1) (An)


(A0) ( C )
( C ) (A7)

10/5/2019
Logical Instructions
 RR A (An) (An + 1)
(A7) (A0)

 RRC A (An) (An + 1)


(A7) (C)
(C) (A0)

10/5/2019
Logical Instructions On Bits

 Similar to logical instructions, these instructions also


perform logical operations.

 The difference is that these operations are performed on


single bits.

10/5/2019
Logical Instructions On Bits
 MNEMONIC DESCRIPTION
 CLR C (C=0)
 CLR bit clear directly addressed bit
 SETB C (C=1)
 SETB bit Set directly
addressed bit
 CPL C (1 = 0, 0 = 1)

 CPL bit Complement directly


addressed bit
10/5/2019
Logical Instructions On Bits
 ANL C, bit Logical AND operation
between Carry bit and directly addressed bit.

 ANL C,/bit Logical AND operation


between Carry bit and complemented direct bit.
 ORL C, bit Logical OR operation
between Carry bit and directly addressed bit.

 ORL C,/bit Logical OR operation


between Carry bit and complement direct bit.
10/5/2019
Logical Instructions On Bits
 MOV C, bit Move directly addressed
bit to carry bit.

 MOV bit, C Move Carry bit to directly


addressed bit.

10/5/2019
Program Flow Control Instructions
 In this group, instructions are related to the flow of the
program, these are used to control the operation like, JUMP
and CALL instructions.

 Some instructions are used to introduce delay in the


program, halt the program-looping as well as instructions
for conditional and unconditional jump.

10/5/2019
Program Flow Control Instructions
Call instruction is used to call a subroutine. Subroutines are
often used to perform frequently needed task.
 MNEMONIC DESCRIPTION BYTE
 ACALL adr11 absolute call 2
The target address of the subroutine must be within 2K bytes.
• LCALL adr16 long call 3
• First byte: opcode
• Second and third byte:16 bit address
• The target address of the subroutine must be within 64K bytes
address space of 8051.
• Every subroutine needs RET as the last instruction.
10/5/2019
Program Flow Control Instructions
 RET return from subroutine 1

 RETI Return from Interrupt 1

10/5/2019
Program Flow Control Instructions-
unconditional jump instructions
 LJMP addr16 (PC) addr15-0

The 2 byte target address allows jump to any memory location


from 0000 to FFFFH.

 SJMP addr short jump from


(from -128 to +127 locations in
relation to current PC)

10/5/2019
Program Flow Control Instructions-
conditional
 JC lab Jump if carry, jumps if C=1

 JNC lab Jump if no carry, jumps if C=0


The carry flag bit in PSW register is used to make the decision.
 JB bit, lab Jump if addressed bit is set. Short jump.
 JBC bit, lab Jump if addressed bit is set and clear it.
Short jump.

10/5/2019
Program Flow Control Instructions
 JMP @A + DPTR (PC) (A) + (DPTR)

 JZ label Jump if A=0


Example: MOV A, R0 ;A=R0
JZ OVER ;jump if A=0
OVER:
Note: JZ can be used only for A
 JNZ Jump if A not= ZERO
 CJNE A, Rx, lab Compare the contents
of acc. And directly addressed register Rx. Jump if they are
different. Short jump.
10/5/2019
Program Flow Control Instructions
 CJNE A, #X, lab compare and Jump if not equal 3
The magnitude of the source byte and destination byte are
compared .If they are not equal ,it jumps to the target
address.
• CJNE @ Ri, # x, lab

10/5/2019
Program Flow Control Instructions
 Looping instructions-repeating a sequence of instruction for
certain number of times.
 In this instruction both the register decrement and the decision
to jump are combined.

 DJNZ Rn , rel (PC) (PC) + 2


(Rn) (Rn) - 1
IF (Rn) > 0 or (Rn) < 0
THEN (PC) (PC) + rel

10/5/2019
 NOP No operation 1
 This performs no operation and execution continues with the
next instruction. It is sometimes used for time delays to waste
clock cycles.

10/5/2019
Summary
 Instruction set.
 Addressing modes.
 Data transfer instruction.
 Arithmetic instruction.
 Logical instruction.
 Logical operation on bits.

10/5/2019

Potrebbero piacerti anche