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SILICON ON INSULATOR(SOI PROCESS)

• To improve speed
• Closer packing of p and n transistors
• Absence of latch up problems
• Lower parasitic to substrate capacitance
• Latch-UP is the generation of a low-
impedance path in CMOS chips between the
power supply and the ground rails due to
interaction of parasitic pnp and npn bipolar
transistors.
• Silicon-on-insulator (SOI) is a semiconductor
structure consisting of a layer of single
crystalline silicon separated from the bulk
substrate by a thin layer of insulator.
• The SOI structure was created for the first
time using silicon on sapphire.
• SOI technology was developed during the
1980s for high-frequency applications
Contd..
• A thin film (7-8 micrometre) of very lightly
doped n-type Si is grown over an insulator.

• An anisotrophic etch is used to etch away the


Si except where a diffusion will be needed.
Contd..
• The p-islands are formed by masking the n-
islands with a photoresist. A p-type-boron is
implanted.
• The p-islands are then covered by photo resist
and an n-type-phosphorus is implanted to
form n-islands.
• A thin oxide layer (100-200A)is grown over all
the Si structures.
• Polysilicon film is deposited over the oxide.
• Polysilicon is then patterned by photomasking
and is etched.This defines the polysilicon layer.
• Form the n-doped source and drain of the n-
channel devices in the p-islands.
• The n-islands are covered with a photoresist
and n-type dopant phosphorus is implanted
• The p-channel devices are formed by masking
the p-islands and implanting a p-type dopant
such as boron.
• The metallization layer is formed next by
evaporating aluminium over the entire
surface.
• It flow through the contact cuts to make
contact with the diffusion and polysilicon
regions.
• A layer of phosphorus glass or silicon dioxide
is deposited over the entire structure
• The glass is etched at contact cut locations.
Advantages of SOI Process
• Transistor structures are placed denser.
• Lower substrate capacitance
• No Latch-up because of the isolation of p-
substrate and n-substrate by the insulating
substrate.
• Because there is no conducting substrate,
there are no body-effect problems.
• (the voltage of the substrate w.r.t. the source
of a CMOS device.)
Twin –tub process
TWIN-TUB PROCESS
• It provides optimization of p and n transistors
• Threshold voltage, bodyeffect, gain of n and
p-devices to be independently optimized
steps
• Starting material is n+ or p+ substrate with a
lightly doped epitaxial layer which is used for
protection against latch-up.
• 1. Tub Formation
• 2.Thin-oxide Formation
• 3.Source and Drain implantations
• 4. Contact cut definition
• 5. Metallization