Junction Field Effect Transistor

(JFET)
 Introduction (FET)

• Field-effect transistor (FET) are important devices such

as BJTs
• Also used as amplifier and logic switches
• What is the difference between JFET and BJT?

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in

 Ic   Ib I d  ? Vgs

BJT is Current-controlled FET is Voltage-controlled

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 Field Effect Transistor

JFET MOSFET
MESFET
or
IGFET
n-Channel p-Channel

Enhancement Depletion
MOSFET MOSFET

n-Channel p-Channel n-Channel p-Channel

EMOSFET EMOSFET DMOSFET DMOSFET

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 BJT Vs FET
1. High input impedance (M)

2. FET is unipolar – uses only one type of current carrier

3. Less noise compare to BJT

4. Temperature stable than BJT

5. Smaller than BJT

6. Can be fabricated with fewer processing steps

7. Usually use as an Amplifier and logic switch

8. Easy to damage than BJT

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 N-channel JFET
– Major structure is n-type material (channel)
between embedded p-type material to form p-n
junction.

– In the normal operation of an n-channel device,

the Drain (D) is positive with respect to the
Source (S). Current flows into the Drain (D),
through the channel, and out of the Source (S).

– Because the resistance of the channel depends

on the gate-to-source voltage (VGS), the drain
current (ID) is controlled by that voltage

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 N-channel JFET

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 JFET Characteristics
1. Drain Characteristics
Vds to Id for a constant V
gs

2. Transfer Characteristics

Vgs to Id

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Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 JFET-Drain Characteristics
1. Vgs =0; Vds =0
2. Vgs =0; Vds  0
• Linear potential drop across the channel.
• Depletion region penetrates more into channel nearer to
drain more than source.
• Drain current increases linearly till pinch-off voltage.
• Beyond pinch off voltage current remains constant (I DSS.)
• Channel resistance increases.
• After certain value JFET Breaks down
3. Vgs < 0; Vds  0 4. Vgs < 0; Vds  0
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JFET for VGS = 0 V and 0<VDS<|Vp|

Channel becomes narrower as VDS is increased

 ID versus VDS

for VGS = 0 V and 0<VDS<|Vp|

JFET Characteristic Curve

Pinch-off (VGS = 0 V, VDS = VP).
 JFET for

(Application of a negative voltage to the gate of a JFET)

 JFET Characteristic Curve
• For negative values of VGS, the gate-to-channel junction is reverse
biased even with VDS=0
• Thus, the initial resistance of channel is higher.
• The resistance value is under the control of VGS
• If VGS = pinch-off voltage(VP)
• The device is in cutoff (VGS=VGS(off) = VP)
• The region where ID constant – the saturation/pinch-off region
• The region where ID depends on VDS is called the linear/ohmic
region
p-Channel JFET
N-Channel JFET characteristics

Ohmic Saturation
 Transfer Characteristics

JFET Transfer Characteristic Curve JFET Characteristic Curve

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 Transfer Characteristics..
In JFET, the relationship between VGS (input voltage) and
ID (output current) is used to define the transfer
characteristics. It is called as Shockley’s Equation:

2
 VGS 
ID = IDSS  1 -  VP=VGS (OFF)
 VP 

Is it a square law device?

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in

 Transfer Characteristics…
• Defined by Shockley’s equation:
2
 V 
I D  I DSS 1  GS  VP  VGS ( off )
 VGS 
 ( off ) 

• Relationship between ID and VGS.

• Obtaining transfer characteristic curve axis point from

Shockley:
– When VGS = 0 V, ID = IDSS
– When VGS = VGS(off) or Vp, ID = 0 mA

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in

 Problem
For a JFET, if I DSS  10 mA and VGss(off)   4V.
Determine drain current ...
for a. VGS = 0V,
b. VGS = -1Vand
c. VGS = - 4V.

Ans:
a.10 mA b.5.625mA c.0mA
JFET MATH MODELS
 DC Load Line
The dc load line for a JFET can be
easily drawn by remembering the
following two points
(i) At ID = 0,
VDS = VDD
(ii) At VDS = 0,
ID = VDD/RD
Q Point is situated in the middle of
the load line  VDD 
VDD  
  
VDSQ 2
2 I DQ
RD
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 Problem

Estimate Quiescent point of

the circuit

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 Session 2

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 Biasing of JFET
Fixing VDS and ID

Biasing methods
1. Fixed Bias

2. Voltage Divider bias

3. Self bias

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in

 Fixed Bias
IG =0  VGS = -VGG

2 2
 VGS   VGG 
ID =IDSS 1-   IDSS 1+  ..(1)
 VP   VP 

VDD -ID R D -VDS =0

VDS  VD  VDD -ID R D ...(2)

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 Problem
Determine the following for the network of Fig.
6.6.
(a) VGSQ. =-2V
(b) IDQ. =5.625mA
(c) VDS. =4.75V
(d) VD. = 4.75V
(e) VG.
=-2V
(f) VS.
=0V

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 Voltage Divider Bias

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 Problem

Determine the following

for the network of Fig.
(a) IDQ = 2.4mA
(b)VGSQ. = -1.8V
(c) VD. = 10.24V
(d) VS. = 3.6V
(e) VDS. = 6.64V
(f) VDG. = 8.42V

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in

 Determine the following for
the network of Fig.
(a) IDQ and VGSQ.
(b) VDS.
(c) VD.
(d) VS.

Assess the difference between the remaining biasing circuits and this
ckt?
Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 Modeling of JFET
Small signal- low frequency modeling parameters
1.Transconductance
ΔID -2 IDSS  VGS  -2 IDSS ID
gm = = 1 -  =
ΔVGS VDS Constant
VP  VGS(off)  VP IDSS
2. Dynamic drain resistance or Drain to source resistance
(slope of the drain characteristic in the pinch-off region and inverse of the
output admittance yos)
1 ΔVDS
rd = 
yos ΔI D VG SConstant
3. Amplification factor
ΔVDS
μ= =g m rd
ΔVGS ID Constant
4. DC Drain resistance
VDS
R DS =
ID
Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 Problem
a. For an N-channel JFET, IDSS
= 8.7 mA, VP = –3 V, VGS = –
1 V. Find the values of
(i) ID =3.87A
(ii) gm =3.87mS
b. Determine the magnitude of
gm for a JFET with IDSS=
8mA and VP =4 V at the
following dc bias points:
(a) VGS=0.5 V. =3.5mS
(b) VGS=1.5 V. =2.57mS
(c) VGS=2.5 V. =1.5mS

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 SMALL-SIGNAL
LOW FREQUENCY MODEL
1. The gate-to-source voltage controls the drain-to-source
(channel) current of an FET.

Δ I D =g m ΔVGS  id =g m vgs
2. Channel Resistance exists between drain and source

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in

 SMALL-SIGNAL
HIGH FREQUENCY MODEL
Need for Introducing other elements
1. Various regions of JFET structure acts as a parallel plate
capacitors

What are they … Guess?

(Cgs, Cds, Cgd and Cgs >> Cds ), To be modeled as Voltage
dependant capacitors. Cgso Cgdo
Cgs = m ;Cgd = m
 Vgs   Vgd 
1+  1+ 
 ψ0   ψ0 
2.The majority carriers require a finite transition time to cross the
source to gate channel.

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 Equivalent Circuit

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 CS FET Amplifier- Fixed bias
(Low/Mid frequency and small signal)

Zi =R G Av = - g m (rd / / R D )  - g m R D
Zo = R D // rd  R D  rd  10R D 
Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 Problem
The fixed-bias configuration of Example 6.1 had
an operating point defined by VGSQ=2 V and
IDQ = 5.625 mA, with IDSS =10 mA and VP8 V.
The network is redrawn as Fig. 9.14 with an
applied signal Vi. The value of yos is provided as
40 S.
=1.88mS
(a) Determine gm.
= 25kΩ
(b) Find rd.
= 1MΩ
(c) Determine Zi.
= 1.85kΩ
(d) Calculate Zo.
=-3.48
(e) Determine the voltage gain Av.
(f) Determine Av ignoring the effects of rd.
=-3.86
Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 High Frequency Equivalent of CS

G D

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 Analysis
1. if Vi=0 and viewing from o/p to get Norton's equuivalent ckt
1
Output Admittance Y0   YL +g d +Yds +Ygd
Z0
I=  -g m +Ygd  Vi

I Zo I -g m +Ygd
2. Voltage Gain Av=  
Vi Vi Yo YL +g d +Yds +Ygd
By the application of Miller’s theorem to Gate to drain

3. Input Admittance Y0 =Ygs +(1-A v )Ygd

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 Voltage divider Bias

v0
Zi  R1 / / R2 Av = = - g m (rd / / R D )  - g m R D
Z o  rd / / RD vi

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 FET Configurations

Common Source

Common Drain

Common Gate

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 DC Analysis of
Common Drain or Source Follower
Equivalent to Emitter follower of BJT

Zi  RG
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 Z0
to makeVi =0 , Gate terminal is to be connected to ground hence Vgs = - Vo
From KCLto o/p node
g m vgs +I0 =I rd +I R s
1 1
 I0  V0 (  )  g m vgs
rd R s
1 1
 V0 (   gm )
rd R s
1
V0  1 1 
Z0      g m    R s / /g m 1 
I 0  rd R s 

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in

 AV
From o/p loop
v0  g m vgs  rd / / Rs 

But from perimeter of the loop vgs = vi -vo

 v0  g m  vi -vo  rd / / Rs 

vo g m  rd / / Rs  g m Rs
Av   
vi 1  g m  rd / / Rs  1  g m Rs

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in

 Problem
A dc analysis of the source-follower
network of Fig will result in
VGSQ =2.86 V and IDQ =4.56 mA.
(a) Determine gm. -2 IDSS 1 - VGS   2.28mS
 
VP  VP 
1
(b) Find rd.  40k 
y os
(c) Determine Zi. 1M 

(d) Calculate Zo with and without rd.

Compare results.
rd / / Rs / / g m 1  365.69
(e) Determine Av with and without rd. A  vo  g m  rd / / Rs   g m Rs  0.83
vi 1  g m  rd / / Rs  1  g m Rs
v
Compare results.
Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 HOME ASSIGNMENT
a. Develop the same analogy
for Common gate
Configuration
b. If VGSQ=2.2 V and IDQ=2.03 mA:
(a) Determine gm.
(b) Find rd.
(c) Calculate Zi with and without rd.
Compare results.
(d) Find Zo with and without rd.
Compare results.
(e) Determine Vo with and without rd.
Compare results.

Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in

 Enhancement MOSFET
Metal

SiO2
Source

P type Substrate
Channel

Drain
Appearing like two diodes connected back to back
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 Circuit Symbol

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 E-MOSFET-Drain Characteristics
1. Vgs =0; Vds =0
2. Vds =0; Vgs  0.. Creating Channel
• Formation of inversion layer
• At Vgs=Vt sufficient number charges available to form
channel. i.e 0<Vgs<Vt Cut off region
• For over drive voltage Vgs>Vt , a proportionate charge will
be induced in the channel
3.  
Vgs >Vt ; 0 <Vds  Vgs -Vt ...Linear ohmic
W
Id =2 k n (VGS -Vt )VDS ; k n  nCox
L
4.  
Vgs >Vt ; 0 < large Vds  Vgs -Vt ...Non Linear ohmic
5.  
Vgs >Vt ;Vds  Vgs -Vt ...Channel Pinch off, Saturation Id =k n (VGS -Vt )2
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Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 Depletion MOSFET

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Field Effect Transistors Dr G V Subbarao gvs0raos@kluniversity.in
 Other effects
Body effect
• Body connected to Source
• Connected to the most negative power supply.
– Depletion region will be widened
– Reduces Channel depth
– Resulting in an increase in threshold Voltage
Temperature Effect
Threshold Voltage decreases by 2 mV/0C

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 MOSFET Biasing
Fixing VGS Fixing VGS and a Drain to Gate resistance
Fix VGS to get resistance at source
the required ID

If IG =0 
I D RD  VGS  VDD

I D  VGS  ID  I D  VGS  I D 
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