TIMING ISSUES IN DIGITAL CIRCUITS:

SYNCHRONOUS DESIGN

Presented by Presented to
Shruti Shreya Dr Anupama Mehra
M. Tech (VLSI)
 Some Basics
The clock is either provided from off chip or is generated on
chip.

From a central point, this clock is then distributed using

multiple matched paths to low level elements. The paths include:
Wiring, Distributed Buffers

Mismatches in the clock distribution may be characterized as:

Systematic: Can be corrected through design
Random: Difficult or impossible to model
Static: Do not change with time
Time Varying: Change with time
 Sources of Skew and Jitter

Skew and jitter sources in synchronous clock distribution.

Clock Signal Generation
Clock generator is a voltage controlled oscillator.
This is an analog circuit that is sensitive to device noise and power
supply variations.
These sources of noise can cause clock jitter.

Manufacturing Device Variations

Device parameters such as oxide thickness, lateral dimensions and
doping levels vary across the chip.
This causes mismatch in the various clock paths which can lead to clock
skew.

Interconnect Variations
Differences in the thickness and width of interconnect cause mismatch in
the clock paths.
Since this variation is static, it contributes to clock skew.
Environmental Variations
The primary contributors to environmental variations: temperature and power supply.
Temperature: is thought to significantly impact skew. This is because all the
modeling is done with the worst case temperature variation, and although on chip
temperature varies with time, it is relatively slow.
Power supply
• Slow (causing skew)
• Fast (causing jitter)

Capacitive Coupling
This can also contribute to clock uncertainty. The major sources are:
•Coupling between clock lines and adjacent wires
•Variations in gate capacitance
The coupling can change based on the direction of the changes in the signal.
Load capacitance changes based on the state of the buffers and so forth.
Since the effects are arbitrary, this contributes to jitter.
 Clock-Distribution Techniques
H-tree network
The clock is routed to a central point
on the chip and balanced paths.

Useful for regular-array networks in

which all elements are identical and
the clock can be distributed as a binary
tree.

Ideally, if each path is balanced, the

clock skew is zero.
RC trees
Represents a floorplan that distributes the clock signal so that the interconnections
carrying the clock signals to the functional sub-blocks are of equal length.

The chip is partitioned into ten

balanced load segments (tiles).

The global clock driver distributes

the clock to tile drivers located at the
dots in the figure.

A lower level RC-matched tree is

used to drive 580 additional drivers
inside each tile.
An example RC-matched distribution for
an IBM Microprocessor.
Grid structure
Used in the final stage of clock network to distribute the clock to
the clocking element loads.

 This can only be used for small grids.

Advantage: It allows for late design changes since the clock is

easily accessible at various points on the die.

Disadvantage: The power dissipation since the structure

has a lot of unnecessary interconnect.
 Latch-Based Clocking

The use of a latch based methodology enables more flexible timing, allowing one
stage to pass slack to or steal time from following stages.

The methodology involves adding logic between latches of a master-slave flip-flop.

Advantage: Slack borrowing

Slack passing happens due to the level sensitive nature of latches.

Latch-based design in which transparent latches are separated by combinational logic.