Chapter 3c

Timing Arc of inverter cell

 Delay value computation
 The delay values have a direct correlation with the
 Load capacitance
 Larger the load capacitance, the larger the delay
 Input transition time
 Increases with increasing Transition time (in most cases)
 Exception : input threshold (used for measuring delay) significantly different
from the internal switching point of the cell
 Delay may show non-monotonic behaviour
 Hi Tr may show Low Delay (if o/p lightly loaded)
 Output Slew
 The slew at the cell output of a cell
depends mainly on
 Output capacitance
 Output transition time increases with
output load
 Large slew at the input can improve at the
output depending upon
 Cell type
 Output load
Rise and fall transition times
Linear delay model
 Simple timing model
 Delay and the o/p transition time of the cell represented as:
 Linear functions of the two parameters:
 Input transition time
 Output load capacitance
 General form of the linear model
 D = D0 + D1 * S + D2 * C
 D0, D1, D2 : Constants
 S : Input Transition time
 C: Output load capacitance
 Linear delay models: Not accurate over the range of input
transition time and output capacitance for submicron tech
Non Linear delay model
 Most Cell Libraries include table models for different timing
arcs of cells
 An NLDM model for delay is presented in a two-dimensional
form with two ind. variables
 the input transition time
 Output load capacitance
 Table shows :
 rising and falling delay models for the timing arc from pin INP1
to pin OUT
 Max_transition allowed at pin OUT
Transition Time
 The NLDM models are also used transition time at the
output of a cell dependent on
 Input transition time
 Output load
 Separate Tables exist for calculating for output transition
times for fall and rise
 Types of timings in delay tables
 The transition times are measured based on the specific slew
thresholds, usually 10%-90% of the power supply
 An inverter cell with an NLDM model has the following tables:
 Rise delay -> cell_rise table
 Fall delay -> cell_fall table
 Rise transition -> rise_transition
 Fall transition -> fall_transition
 Question: difference between Rise delay and rise transition
 There is a separate liberty user guide for understanding etymology
of .lib file
Delays
Definition of indices

 Alternate way
Table for Cell Rise and Fall
Transition times
 Example
 Rise delay from :
 cell_rise table for 15ps input transition time (falling)
 10fF load,
 Fall delay from
 cell_fall table for 20ps input transition time (rising) and 10fF load
 How to select i/p trans. Time , Falling or rising ?
 Unateness
 Threshold Specifications and Slew
Derating
 previous generation libraries (0.25mm or older) used 10% and 90% as
measurement thresholds for slew or transition time
 slew thresholds correspond to the linear portion of the waveform
 New technologies : linear portion 30% -70%
 New generation.lib : slew measurement 30%-70%
 For equivalency calculation, slew derate factor :
 the transition times 30%-70% doubled for populating the library
 slew derate factor which is typically specified as 0.5
Example

 Here,
 Transition times in the library tables * 0.5
= transition times slew threshold (30-70)
If slew derate factor specified
Timing Models - Combinational Cells
For two-input and cell,
 Four delays:
 A -> Z: Output rise
 A -> Z: Output fall
 B -> Z: Output rise
 B -> Z: Output fall
 Four output transition times as well
 In library 4 timing infos from one i/p to o/p are combined
 For non-unate models : State dependent models are
presented in .lib file
 Timing Models - Sequential Cells
 For synchronous inputs, such as pin D (or
SI, SE), timing arcs:
 Setup check arc (rising and falling)
 Hold check arc (rising and falling)
 For asynchronous inputs, such as pin
CDN, timing arcs:
 Recovery check arc
 Removal check arc
 For synchronous outputs of a FF such as
pins Q or QN, timing arcs:
 CK-to-output propagation delay arc (rising
and falling)
Timing arcs w.r.t active clk edge
Synchronous Checks: Setup and Hold
 Timing checks validate if data input is stable around the
active clock edge
 Setup time: Min. time b/f the active clk, data input must be
stable
 Time b/w: D crossing threshold -> Clk crossing th.
 Hold Time: Min.Time D, should be stable a/f act. Clk edge
 Act. Clk Edge:Rising or falling->causes data capture
Examples from library: setup_rising
Example: hold_rising
Details of indices
 Constrained Pin : Data input pin
 Related Pin : related_pin() , CK
Negative Values in Setup and Hold
Checks
 Some hold values are negative
 Happens when the path from FF pin to the internal latch
point for the data is longer than the corresponding path for
the clock
 A negative hold check implies that the data pin of the flip-
flop can change ahead of the clock pin and still meet the hold
time check
 Setup values can be –ve :
 data can change after the clock pin
 Can both setup and hold be negative?
 sum of setup and hold values should be positive
 For FF : -ve hold time helpful on scan data input pins
 Gives flexibility w.r.t clock skew
 Can eliminate the need for most buffer insertion for fixing hold
violations in scan mode
Asynchronous Checks
 Checks governing asynch pins
 Recovery
 Removal
 Examples : asynchronous clear or asynchronous set
 Asynch. Inputs override synchronous behavior of the cell.
 If asynchronous pin -> active
 o/p governed by the asynchronous pin
 not by the clock latching in the data inputs.
 When the asynchronous pin -> inactive,
 active edge of the clock starts latching in the data input
 The checks verify that the
 asynchronous pin has returned unambiguously to an inactive state at
the next active clock edge
Recovery and removal times
 Recovery time
 Min time, an asynchronous input is stable after being de-
asserted before the next active clock edge
 Removal time
 Min time after an active clock edge that the asynchronous pin
must remain active before it can be de-asserted
 Pulse width check
 there is a check which ensures that the pulse width at an
input pin of a cell meets the minimum requirement e.g. at
CK pin
Propagation Delay
 The propagation delay of a sequential cell is from the active edge
of the clock to a rising or falling edge on the output
State Dependent models
 In non unate cases, where an output depends upon other
inputs
 timing behaviors can be different depending upon the state of
other inputs of the block.
 Multiple timing models depending upon the states of the pins
are described.
 Such models are referred to as state-dependent models
XOR, XNOR and Sequential Cells
 The timing model from A1 to Z when A2 is logic-0 is specified
 The state-dependent condition is specified using the when
condition.While the cell model excerpt only illustrates the
cell_rise delay, other timing models
 (cell_fall, rise_transition and fall_transition tables) are also
specified with the same when condition. A separate timing model is
specified for the other when condition - for the case when A2 is
logic-1.
 If there is no non-state-dependent model for the hold
constraint, there will not be any active hold constraint
Leakage power representation
Interface Timing Model for a Black Box
Timing model
The interface timing model not intended to capture the internal
timing of the black box, but only the timing of its interfaces
 I/O to O/p combinational arc: Direct combinational path from
input to output, such as from the input port F
 Input sequential arc: Setup or hold time for the i/p connected to a
D-pin of the flip-flop.
 May be a combinational logic from the input of the block
before it is connected to a D-pin of the flip-flop
 An example of this is a setup check at port DIN with respect to
clock ACLK
General timing values
 I/O to O/P timing arcs for combinational logic paths
 Setup and hold timing arcs from the synchronous inputs to the
related clock pins
 Recovery and removal timing arcs for the asynchronous inputs to the
related clock pins
 Output propagation delay from clock pins to the output pins.
Advanced Timing Modeling
 NLDM : Represent delay thu the timing arcs based upon
 o/p load capacitance
 i/p transition time
 Assumption : O/p loading capacitive
 Realistically, load at cell O/P :
 Capacitance
 Interconnect Resistance
 Delay calc. Methodologies
 NLDM + effective capacitance (eq. Cap with RC effect)
 Feature size inaccuracy due to RC effect
Modelling Approaches to include RC
effect
 O/p stage of the driver by an equivalent current
source
 CCS (Composite Current Source)
 Cell output drivers modelled by using a time-
varying and voltage-dependent current source
 ECSM (Effective Current Source Model)
 Timing information is provided by specifying
detailed models for the receiver pin capacitance
R/x Pin capacitance
 receiver capacitance varies at different points on the
transitioning waveform due to
 Interconnect
 RC and the equivalent input non-linear capacitance (miller eff.)
 Methods of modeling, R/x pin cap. Can be spec.
 At The pin level (NLDM), all timing arcs use cap. the timing arc
level
 At timing arc level, different capacitance models can
be specified for different timing arcs
Specifying Capacitance at the Pin Level

 Receiver_capacitance1_rise , the receiver_capacitance2_rise

specifies the rise capacitance for the trailing portion of the input
rising waveform
Specifying Capacitance at the Timing
Arc Level
Models for cross talk analysis
 There are models for cross talk noise
 They are beyond the scope of my mind
Power dissipation modeling
 Standard cell contains :
 Standby or Leakage power
 Active power (related with activity of the design)
 Active power
 Activity at the input and output pin of the cell
 Due to
 Output Switching power : Charging of the output load
 Indep. Of cell type
 Dep. On capacitive load, frequency of switching and the power supply of
the cell
 Internal switching Power
 Dep. On type of cell
 Incl. In the cell library
Internal switching power in lib (inv.)
Double Counting Clock Pin Power?
 Note that a flip-flop also contains the power dissipation due
to CLK->Q transition.
 It is thus important that the values in the CLK->Q power
specification tables do not include the contribution due to the
CLK internal p
Leakage Power
 Most standard cells are designed such that the power is
dissipated only
when the output or state changes.
 Power dissipated when
 The cell is powered but there is no activity is due to non-zero
leakage current.
 It is due to subthreshold current for MOS devices or due to
tunneling current through the gate oxide.
 Due to technology shrinks, the leakage power is becoming
significant
In lib leakage power
Other Attributes in Cell Library
 Area Specification
 The area specification provides the area of a cell or
cell group
 area : 2.35;
 Function Specification

 SDF Condition
 Supports the Standard Delay Format (SDF) file generation and
condition matching during backannotation.
 when specifies the condition for the state-dependent models for timing
analysis
 SDF used for state-dependent timing usage for SDF annotation
Characterization and Operating
Conditions
 A cell library specifies the characterization and operating
conditions under which the library is created
Characterization and Operating
Conditions
 A cell library specifies the characterization and operating
conditions under which the library is created
The nominal environmental
specify the process, voltage and
temperature under which the
library was characterized
Characterization and Operating
Conditions
 A cell library specifies the characterization and operating
conditions under which the library is created
•Specify the conditions under
which the cells will get used.
•If the operating conditions are
different, the timing Values need
to be derated;
•Accomplished by using the
derating factor (k-factors)
 Process Variable?
 Process is not a quantifiable quantity
 It is likely to be one of
 Slow,
 Typical
 Fast
 Purpose: Digital characterization and verification.
 Process value of 1.0 (or any other value) mean?
 The library characterization : time-consuming process (can take weeks)
 Allows a library characterized at a specific process corner be used for timing
calculation for a different process corner
 The k-factors for process can be used to derate the delays from the characterized
process to the target process.
 Introduces inaccuracy during timing calculation
 Derating across process conditions is especially inaccurate and is rarely employed.
 The only function of specifying different process values (say 1.0 or any other) is
to allow derating across conditions which is rarely (if ever) employed.
Derating using K-factors

 etc.
-ve and positive k
 k_volt factors : –ve , the delays reduce with increasing voltage
supply, Characterization and Operating Conditions
 k_temp factors +ve : delays normally increase with increasing
temperature (with exceptions) .
 The k-factors Usage
Library Units