UNIT -2

Analysis and Design of

Combinational Logic Circuits -
 Topics to be covered :
 Combinational logic :Definition,
 Difference between combinational and
sequential
 Various types of adders
 Combinational Circuit
A combinational circuit consists of
 Input variables

 Logic gates

 Output variables

 Block diagram of Combinational Circuit

Combinational v.s Sequential Circuits
Logic circuits may be combinational or sequential
Combinational circuits:
 Consist of logic gates only.

 Outputs are determined from the present values of inputs.

 Does not consist of memory element.

Sequential circuits:
 Consist of logic gates and storage elements

 Outputs are a function of the inputs and the state of the storage
elements.
 Depend not only on present inputs, but also on past values

 Consist of memory element

 ADDERS
 Binary Adder
 Half Adder
 Full Adder

 Full adder using half adder

 Ripple Carry Adder

 Carry look ahead adder

 Decimal Addition
 BCD adder
 1-bit Adder (HALF ADDER)
 Performs the addition of two binary bits.
 Four possible operations:
 0+0=0
 0+1=1
 1+0=1
 1+1=10

 Circuit implementation requires 2 outputs; one

to indicate the sum and another to indicate the
carry.
 Half Adder
 Performs 1-bit addition. Truth Table
 Inputs: A0, B0 A0 B0 S0 C1
 Outputs: S0, C1 0 0 0 0
 Index indicates significance, 0 1 1 0
0 is for LSB and 1 is for the
next higher significant bit. 1 0 1 0
 Boolean equations: 1 1 0 1
 S0 = A0B0’+A0’B0 = A0  B0
 C1 = A0B0
 Half Adder (cont.)
 S0 = A0B0’+A0’B0 = A0 B0
 C1 = A0B0

Block Diagram Logic Diagram

A0 B0
A0
S0
1 bit B0
C1
half adder

C1
S0
 TWO DIFFERENT IMPLEMENTATIONS OF HALF
ADDER
T IMPLEMENTATIONS OF HALF ADDER

9
 Full Adder
 Full adder (for higher-order bit addition)
 Combinational circuit that performs the
additions of 3 bits (two bits and a carry-in
bit)
Ai Bi

1 bit
Ci+1 Ci
full adder

Si
 Full Adder (cont.)
 The K-maps for
Ai Bi Ci Si Ci+1
 Ci+1: BiCi
Ai 0 0 0 0 0
0 0 10 0 0 1 1 0
0 1 0 1 0
0 1 1 1
0 1 1 0 1
1 0 0 1 0
BiCi
 Si: 1 0 1 0 1
Ai
0 1 0 1 1 1 0 0 1
1 1 1 1 1
1 0 1 0
 Full Adder (cont.)
Boolean equations:
 Ci+1 = AiBi + AiCi + BiCi
 Si = AiBi’ Ci’ + Ai’Bi’Ci + Ai’BiCi’ + AiBiCi
= Ai  Bi  Ci
You can design full adder circuit directly from
the above equations (requires 3 ANDs and 1 OR
for Ci+1 and 2 XORs for Si)
DIGITAL SYSTEMS TCE1111

Implementation of Full Adder using AND-OR

Gate Network

13
 Full Adder using 2 Half Adders
 A full adder can also be realized with two half adders and an
OR gate, since Ci+1 can also be expressed as:
 Ci+1 = AiBiCi + AiBi’Ci + Ai’BiCi + AiBiCi’
= AiBi + (AiBi’ + Ai’Bi)Ci
= AiBi + (Ai  Bi)Ci
 and Si = Ai  Bi  Ci

Ai
Bi Si

Ci+1

Ci
DIGITAL SYSTEMS TCE1111

Implementation of Full Adder using

Two Half Adders (2)

X S

Z
C

15
 n-bit Combinational Adders
 Perform parallel multi-bit addition
 Ripple Carry Adder
 Simple design
 n-bit Addition
 Design an n-bit binary adder which performs the
addition of two n-bit binary numbers and generates a
n-bit sum and a carry out.

 Example: Let n=4

Cout C3 C2 C1 C0 1 1 0 1 0
A3 A2 A1 A0 1 1 0 1
+ B3 B2 B1 B0 +1 1 0 1
--------------------- ----------
S3 S2 S1 S0 1 0 1 0
 PARALLEL ADDER

 Parallel Adder is a digital circuit that produces

the arithmetic sum of 2 binary numbers.
 Constructed with full adders connected in
cascade, with output carry from each full adder
connected to the input carry of next full adder
in the chain.
 The augend bits of A and the addend bits of B
are designated by subscript numbers from right
to left, with subscript 1 denoting the least
significant bit.
 The carries are connected in a chain through
the full adders.
18
 n-bit Ripple Carry Adder

 Constructed using n 1-bit full adder blocks

in parallel.
 Cascade the full adders so that the carry out
from one becomes the carry in to the next
higher bit position.
Example: 4-bit Ripple Carry Adder
C4 C3 C2 C1 C0
A3 A2 A1 A0
+B3 B2 B1 B0
--------------
S3 S2 S1 S0
 Ripple Carry Adder Delay
 Circuit delay in an n-bit ripple carry adder is determined by the
delay on the carry path from the LSB (C0) to the MSB (Cn).
 Let the delay in a 1-bit FA be Δ. Then, the delay of an n-bit
ripple carry adder is nΔ.
 Logic Symbol Of Four Bit Parallel Adder (4)…

The 4 bit parallel adders can be used to form 8 bit, 12 bit,

16 bit and 32 bit parallel adders.

22
Logic symbol of 8 bit parallel adder (5)

23
Four Bit Parallel Subtractor using
Full Adders

24
4 bit Parallel Four Bit Adder / Subtractor
Circuit using Full Adders

25
DIGITAL SYSTEMS TCE1111

HALF SUBTRACTORS

Half subtractor accepts two binary digits as input (Minuend and

Subtrahend) and produces two outputs, a Difference bit (Di) and
Borrow bit (B0).
Difference Borrow
00 = 0 0
01 = 1 1
10 = 1 0
11 = 0 0

26
DIGITAL SYSTEMS TCE1111
The truth table and the logic symbol for half subtractor

A’B A’B
AB’

27
DIGITAL SYSTEMS TCE1111

Boolean expressions for half subtractor

The difference (Di) output column of the truth table

is an XOR operation.

Di = A  B
The Boolean expression for the borrow (B0) output is

28
DIGITAL SYSTEMS TCE1111

LOGIC DIAGRAM OF HALF SUBTRACTOR

29
DIGITAL SYSTEMS TCE1111

FULL SUBTRACTOR-Truth Table and

Logic Symbol

The FS accepts three inputs including a borrow input (Bin) and

produces a difference output (Di) and a borrow output (B0).

30
DIGITAL SYSTEMS TCE1111

Boolean Expressions for Full Subtractor

A’B’Bin A’B’Bin
A’BBin’ A’BBin’
A’BBin

AB’Bin’

ABBin ABBin

31
DIGITAL SYSTEMS TCE1111

Boolean Expressions for Full Subtractor

Di=
A’B’Bin + A’BBin’ + AB’Bin’ + ABBin
= A’(B’Bin + BBin’) + A(B’ Bin’ + BBin)
= A’(B  Bin) + A(B  Bin)’
= A B Bin

B0

A’B’Bin + A’BBin’ + A’BBin + ABBin

= A’B’Bin + ABBin + A’B(Bin + Bin’)
= Bin( A B)’ + A’B

32
DIGITAL SYSTEMS TCE1111

Boolean Expressions for Full Subtractor

Difference output of the FS can be given by

Di = A  B  Bin

The borrow output of the FS can be derived

by the truth table as follows.

33
DIGITAL SYSTEMS TCE1111
LOGIC DIAGRAM FOR FULL SUBTRACTOR

Di = A  B  Bin

34
 Carry Look ahead Adder

 Alternative design for a combinational n-bit

adder.
 Practical design with reduced delay at the
expense of more complex hardware.
 Derived from a transformation of the ripple
carry adder design.
 Carry Lookahead Adder Design

 Ci+1 = AiBiCi + AiBi’Ci + Ai’BiCi + AiBiCi’

= AiBi + (AiBi’ + Ai’Bi)Ci
= AiBi + (Ai  Bi)Ci

 From a FA, separate between carry generation (a new carry signal

is generated, i.e. Cout=1) and carry propagation (an existing Cin is
propagated to Cout)
 Generate: Gi = AiBi: if 1, Ci+1=1
 Propagate: Pi = Ai  Bi: if 1, Ci+1 = Ci
DIGITAL SYSTEMS TCE1111

Carry Propagation (1)…

• The signal must propagate through the gates

before the correct output sum is available
in the output terminals.
• The total propagation time is equal to the
propagation delay of a typical gates times
the number of gate levels in the circuit.

37
DIGITAL SYSTEMS TCE1111

Full Adder Circuit with P and G (2)

• If we define two new binary variables
Pi = Ai  Bi
Gi = Ai Bi
Then output sum and carry can be expressed as
Si = Pi Ci
Ci+1 = Gi +PiCi
• Gi is called a carry generate and it produces a carry of
1 when both Ai and Bi are 1, regardless of the input
carry Ci
• Pi is called a carry propagate because it is the term
associated with the propagation of the carry from ci to
ci+1.
38
 Block CLA

 Implement:
 C1 = G0+P0 C0
 C2 = G1+P1C1 = G1+P1(G0+P0C0) = G1+P1G0+P1P0C0

 C3 = G2 + P2C2 = G2+P2G1+P2P1G0+P2P1P0C0

 C4 = G3+P3G2+P3P2G1+P3P2P1G0 + P3P2P1P0 C0
= G0-3 + P0-3C0
Group carry generate Group carry propagate
DIGITAL SYSTEMS TCE1111

Carry Lookahead Generator (2)…-Logic

Diagram

C3

C2

C1

40
DIGITAL SYSTEMS TCE1111

4 bit adder with carry lookahead (2)

41
 BCD Adder
 BCD Decimal Adder:
 Requires 8 inputs (4 bits per decimal number)
 5 outputs indicate the decimal sum and the carry
 BCD addition rules: Add 0110 to the sum if it is
greater than 1010 to correct the carry bit
 BCD ADDITION (1)…
 Procedure:
 Step 1: Add the two BCD numbers, using the rules
for binary addition
 Step 2: If a 4-bit sum is equal to or less than 9, it is
a valid BCD number.
 Step 3: If a 4-bit sum is greater than 9, or if a carry
out of the 4-bit group is generated, it is an invalid
result. Add 6 (0110) to the 4-bit sum in order to
skip the six invalid states and return the code to
8421. If a carry results when 6 is added, simply
add the carry to the next 4-bit group. 43
DIGITAL SYSTEMS TCE1111

Block Diagram of a BCD Adder

44
 CODE CONVERTERS
 Code converter is a system which must be
introduced between the two systems if each
uses different codes for the same information.
 Code converter is a system which makes two
system compatible even though both uses
different for information.
 Code converters are specially used for
protecting private information
 Excess-3 and gray codes
 Excess-3 code
 It is a non weighted code.
 In XS-3, numbers are represented as decimal
digits, and each digit is represented by four
bits as the digit value plus 3 (the"excess“
amount).
 The primary advantage of XS-3 coding over
non-biased coding is that a decimal number
can be nines' complemented as easily as a
binary number can be ones' complemented.
 Self complementary or reflective code
 Code Conversion Example
 Convert from BCD code to Excess-3 code.
 The 6 input combinations not listed are don’t cares.
 These values have no meaning in BCD.
 We can arbitrary assign them to 1 or 0.
 Maps for Code Converter
 The six don’t care minterms (10~15) are marked with X.
Maps for Code Converter
Excess-3 to BCD conversion
K map
 Gray code
 It was named after Frank Gray
 It is also called as unit distance code
 Gray code is a reflective binary code
 Gray codes are non weighted and cyclic codes
Binary to gary conversion
GRAY TO BINARY
Truth table
 Binary Comparators
 Single bit comparator
A =B =>A’B’ + AB
A > B = >AB’
A< B = >A’B
 Two-bit comparator compares two binary bits
2 bit comparator
 Multiplexer
 Digital multiplexers provide the digital
equivalent of analog selector switch.
 Multiplexer connects one of n inputs to a
single output line, so that the logical value of
input is transferred to the output.
 One of n input selection is determined by
select line m.
 n=2m
4:1 multiplexer
Realizing higher order mux using
4:1 and 2:1
 Realize 4:1 using 2:1 mux
 Realize 8:1 using 4:1 mux

 Realize 16:1 mux using 4:1 and 8:1

Multiplexers as Boolean function
generators
 design F=∑(0,1,4,6) by using a)8:1 mux b)
4:1 mux
 Implement full adder using 4:1 mux
 Implement the given function
f= ∑(1,3,4,11,12,13,14,15) using a) 8:1 mux
b) 4:1 mux and c) 2:1 mux
 Implement the given function
f= ∑(0,2,4,6,8,10,15) using
a) 8:1 mux
b) 4:1 mux
c) 2:1 mux
 Design full subtractor using 4:1 mux

( Exercise)
 DECODERS
 It is a multiple-input , multiple-output logic
circuit which has n-inputs and 2n outputs.
 It converts data from one format to another.
 Several forms of decoder are:
 2 to 4 line decoder
 3 to 8 line decoder
 4 to 16 line decoder


2 to 4 decoder with enable signal
Truth table of 3 to 8 decoder
 Logic design using decoders
 Implement the following function using a 3 to
8 line decoder.
i. F=∑m(0,4,6,7)

ii. f1 = ∑m(1,2,5,6,7) , f2 = ∑m(1,4,5)

 Implement the following function using a
decoder minimizing the number of inputs to
be summed.
I. f1 = ∑m(1,2,5,6,7) , f2 = ∑m(1,3,4,6,7)
II. f1 = πm(2,3,4,5,7) , f2 = π m(0,2,4,5)
 Implement the following function using a
decoder with active low outputs.
I. f1 = ∑m(1,2,5,6,7) , f2 = ∑m(1,3,4,6,7)
II. f1 = πm(0,1,3,5,6) , f2 = π m(2,3,4,5,7)
III. f1 = πm(1,2,5) , f2 = ∑m(0,1,3,5,7)
DEMULTIPLEXER
What is a Demultiplexer (DEMUX)?
• A DEMUX is a digital switch Demultiplexer
with a single input (source) Block Diagram
and a multiple outputs
(destinations).

DEMUX
• The select lines determine 1 2N
Input Outputs
which output the input is (source) (destinations)

connected to.
• DEMUX Types N
 1-to-2 (1 select line) Select
 1-to-4 (2 select lines) Lines
 1-to-8 (3 select lines)
 1-to-16 (4 select lines)
1-to-4 De-Multiplexer (DEMUX)
D0

DEMUX
D1
IN
D2

D3

B A

B A D0 D1 D2 D3
0 0 IN 0 0 0

0 1 0 IN 0 0

1 0 0 0 IN 0

1 1 0 0 0 IN

74