Multiplexer

module mux1( select, d, q );

input[1:0] select;
input[3:0] d;
output q;

assign q = d[select];

endmodule
 assign signal_name = condition ? expression_T : expression_F;

module mux1( select, d, q );

input[1:0] select;
input[3:0] d;
output q;
assign q = ( select == 0 )? d[0] : ( select == 1 )? d[1] : ( select == 2 )? d[2] : d[3];
endmodule
Multiplexer
module mux2( select, d, q );

input[1:0] select;
input[3:0] d;
output q;
reg q;
always @(d or select)
q = d[select];
endmodule
Multiplexer if( condition )
statement;
module mux1( select, d, q );
input[1:0] select;
input[3:0] d;
output q;
reg q;
always @( select or d )
begin
if( select == 0)
q = d[0];
if( select == 1)
q = d[1];
if( select == 2)
q = d[2];
if( select == 3)
q = d[3];
end
endmodule
Multiplexer
module mux1( select, d, q ); case expression
input[1:0] select; choice1 : sequential statements1
choice2 : sequential statements2
input[3:0] d; ...
output q; [default : sequential statements]
reg q; endcase;
always @( select or d )
begin
case( select )
0 : q = d[0];
1 : q = d[1];
2 : q = d[2];
3 : q = d[3];
endcase
end
endmodule
module mux1( select, d, q );
input[1:0] select;
input[3:0] d;
output q;
reg q;
always @( select or d)
begin
q = ( ~select[0] & ~select[1] & d[0] )
| ( select[0] & ~select[1] & d[1] )
| ( ~select[0] & select[1] & d[2] )
| ( select[0] & select[1] & d[3] );
end
endmodule
`timescale 1ns / 1ps
module block_nonblock();
reg a, b, c, d , e, f ;
// Blocking assignments
initial begin
a = #10 1'b1; // The simulator assigns 1 to a at time 10
b = #20 1'b0; // The simulator assigns 0 to b at time 30
c = #40 1'b1; // The simulator assigns 1 to c at time 70
end
// Nonblocking assignments
initial begin
d <= #10 1'b1; // The simulator assigns 1 to d at time 10
e <= #20 1'b0; // The simulator assigns 0 to e at time 20
f <= #40 1'b1; // The simulator assigns 1 to f at time 40
end
endmodule
module block_nonblock();
reg a, b, c, d , e, f ;
// Blocking assignments
initial begin
#10 a = 1'b1; // The simulator assigns 1 to a at time 10
#20 b = 1'b0; // The simulator assigns 0 to b at time 30
#40 c = 1'b1; // The simulator assigns 1 to c at time 70
end
// Nonblocking assignments
initial begin
#10 d <= 1'b1; // The simulator assigns 1 to d at time 10
#20 e <= 1'b0; // The simulator assigns 0 to e at time 20
#40 f <= 1'b1; // The simulator assigns 1 to f at time 40
end
endmodule
//a 4:1 multiplexer using built-in primitives
module mux_4to1 (d, s, enbl, z1);
input [3:0] d;
input [1:0] s;
input enbl;
output z1;
not inst1 (net1, s[0]),
inst2 (net2, s[1]);
and inst3 (net3, d[0], net1, net2, enbl),
inst4 (net4, d[1], s[0], net2, enbl),
inst5 (net5, d[2], net1, s[1], enbl),
inst6 (net6, d[3], s[0], s[1], enbl);
or inst7 (z1, net3, net4, net5, net6);
endmodule
//mixed-design full adder //behavioral
module full_adder_mixed (a, b, cin, sum, cout); always @ (a or b or cin)
//list inputs and outputs begin
input a, b, cin; cout = cin & (a ^ b) | (a & b);
output sum, cout; end
//define reg and wires //dataflow
reg cout; assign sum = net1 ^ cin;
wire a, b, cin; endmodule
wire sum;
wire net1;
//built-in primitive
xor (net1, a, b);
//example of using a parameter
module param1 (a, b, cin, sum);
parameter width = 8;
input [width-1:0] a, b; //a and b are 8 bits (7:0)
input cin; //cin is a scalar
output [width:0] sum; //sum is 9 bits (8:0)
//to include cout
//inputs default to wire
reg [width:0] sum;
always @ (a or b or cin)
begin
sum = a + b + cin;
end
endmodule
// 8-to-3 priority encoder with active high enable input
module encoder(din, dout);
input [7:0] din;
output [2:0] dout;
reg [2:0] dout;
always @(din)
begin
if (din==8’b00000001) dout=3’b000;
else if (din==8’b0000001X) dout=3’b000;
else if (din==8’b000001XX) dout=3’b010;
else if (din==8’b00001XXX) dout=3’b011;
else if (din==8’b0001XXXX) dout=3’b100;
else if (din==8’b001XXXXX) dout=3’b101;
else if (din==8’b01XXXXXX) dout=3’b110;
else if (din==8’b1XXXXXXX) dout=3’b111;
else dout=3’bX;
end
endmodule
//Verilog module. case (bcd) //case statement
module segment7( 0 : seg = 7'b0000001;
bcd, 1 : seg = 7'b1001111;
seg 2 : seg = 7'b0010010;
); 3 : seg = 7'b0000110;
4 : seg = 7'b1001100;
//Declare inputs,outputs and internal variables. 5 : seg = 7'b0100100;
input [3:0] bcd; 6 : seg = 7'b0100000;
output [6:0] seg; 7 : seg = 7'b0001111;
reg [6:0] seg; 8 : seg = 7'b0000000;
9 : seg = 7'b0000100;
//always block for converting bcd digit into 7 default : seg = 7'b1111111;
segment format endcase
always @(bcd) end
begin
endmodule
4-bit magnitude comparator