Computer Architecture

o CPU
o Main memory unit
o Interconnection of units
o Cache
o Communication between various units
o The instruction format
o Instruction set
o Processor speed
o Multiprocessor systems
o CPU- CENTRAL PROCESSING UNIT

Central processing unit

Control unit Arithmetic logic

unit

Central
Registers
 Processor controls all internal and external
devices and performs arithmetic and logic
operations.
 Operates only binary data(1 s &0s).

ALU

CPU CU

Registers
 A. ALU- Arithmetic / logic unit
1. Arithmetic unit:
Actual computing and carrying out the
arithmetic calculations(at high speed).
2. Logic unit:
logical operation tests three conditions:
1 Equal-to condition
2 less-than condition
3 greater-than condition
B. Registers
Register name functions

Program counter (PC) Keeps the track of next instruction to be

executed.

Instruction register (IR) Holds the instruction to be decoded by

control unit.

Memory address register(MAR) Holds the address of next location in

memory.

Memory buffer register(MBR) Stores data either coming to cpu or data

being transferred by the CPU.

Accumulator (ACC) For storing temporary results and results

produced by arithmetic logic unit.

Data register (DR) For storing operands and other data.

C. Control unit
 Heart of CPU.
 The four basic operations.
 It controls input output devices and transfer the data
to and from the primary storage.
The control unit repeats a set of four basic operations:
1 Fetching
2 Decoding
3 Executing
4 Storing
o Main memory unit
The part of computer which holds data and
instructions for processing.
Primary memory is of two types:
RAM
ROM
RAM- Random Access Memory

 provide the required instruction to the processor.

 volatile in nature

DRAM

RAM

SRAM
ROM- Read Only Memory
 can only be read from any location.
 Stores initial start up instruction and routines in
BIOS.
 Non-volatile
 Firmware
Types:
PROM
EPROM
EEPROM
o INTERCONNECTION OF UNITS
System Bus
 Bus- set of connections between two or more
components , designated to transfer bits of a word
from source to destination.
 multiple paths(lines)
 A bus that connect to all the components (CPU ,
Memory & I/O devices).
 System lines are broadly categorised into three
functional groups:
 Data lines
 Address lines
 Control lines
Bus interconnection
o Cache
 cache is a piece of very fast memory, made from high
speed static RAM that reduces the time of accessing
the data.
 catch up with the processor speed

Cache is classified into three levels:

 Level 1 cache(L1)[primary cache]
• Level 2 cache(L2)[secondary cache]
• Level 3 cache(L3)
o Communication Between Various Units Of A
Computer System
To have proper coordination a reliable mean of
communication is essential
Two major communications between the systems:
 Processor to memory communication
 Processor to I/O devices communication
 Main memory

Address
Data

Instruction and date

{ Cache memory

Address Data

processor

Processor memory communication

Processor to I/O communication
o The instruction format
A computer understands instructions in terms of 0s
and 1s
Number bit

1 0 1 1 0 1 0
{
Operand
Opcode
 Instructions are usually divided into following
types:
 Data transfer instruction (registers or external
main memory)
 Arithmetic instructions
 Logical instructions
 Program control instructions
 I/O instructions
 Instruction cycle
The processor of the system performs the
execution work

picccccc
Instruction Function

ADD Perform addition

SUB Perform subtraction

MUL Perform multiplication

MOV Move the contents from one location to

another.

DIV Perform division

LDA Load the contents of the variable.

JMP Jump to the instruction.

ABS Calculate absolute value

• A simple instruction cycle consists of:
o Instruction set
 To create machine language program
 Embedded in the processor( boundaries of
processors instruction set).
Architectures : CISC- complex instruction set
computers
RISC- reduced instruction set
computers
CISC Architecture

Compiler
HL lang LL lang

 CISC was developed to make compiler

development easy
 To manufacture processor with more extensive
and complex instruction set.
 Most PCs are of CISC processor
 RISC Architecture
 It utilizes a small, highly optimized set of
instructions.
 Simplifies the instruction set-Reduces the
execution time
 Pipelining –overlapping( incorparate registers)
Basis CISC RISC

Instruction set Complex instructions Simple instructions

Program code size smaller Lengthier

Processor size Increased hardware circuitry Reduced hardware circuitry

Memory usage Less memory intensive More memory intensive

Power consumption More power Less power

Heating More heat Less heat

Distinction between the CISC & RISC Processors