005 Fpga Spartan Verilog 2003

Lab 4: FPGA Implementation
Specification
RTL design and

Simulation
Logic Synthesis
Gate Level Simulation
ASIC Layout FPGA Implementation

Lab3-1
張明峰交大資工系
Why Top-Down?
• Design of complex systems
• Reduce time-to-market
– shorten the design verification loop
– focus on functionality
• Easier and cheaper to explore different design option
Lab3-2
RTL Design
• Characteristics
– fully clock driven RTL code with some behavioral constructs
– contain complete functional description
– cycle accurate
• Coding style
– structural description (component connections/net-list)
– data flow description (continuous assignment)
– RTL description (always block)
• combinational RTL
• sequential RTL
Lab3-3
Logic Synthesis
• Translate synthesizable RTL code to gate-level
design
Always @(posedge clk) begin

if(sel1) begin
if(sel2)
out = in1 ;
else
out = in2 ; Gate-level circuits
else if(sel3)
if(sel4)
out = in3 ;
else
out = in4 ;
end
endmodule
Lab3-4
Structural Mapping
Lab3-5
Resource Sharing
• Example
if (op_code ==0)
r=a+c;
else
r=a+b;
• Sharing
– a single ALU for the two additions
– a MUX for the second input of the ALU
• No-Sharing
– two adders for the two additions
– an output MUX to select the output
Lab3-6
Register Inferencing
• Determines which signals must be preserved across
cycle boundaries
– incomplete logic specification (missing branches)
– explicit register instantiation
• always @(posedge clk)
– signal used before assigned
Lab3-7
Two-level Logic Optimization
• AND-OR representations
– easy implementation as PLAs and PLDs
– a key optimization technique
– efficient algorithms and heuristics exist
– in commercial use for several years
– minimize the number of product terms
• Example
– F = XYZ + XY’Z’ + XY’Z + X’YZ + XYZ
– F = XY’ + YZ
Lab3-8
Multi-Level Logic Optimization
• Meet performance or area constraints through
restructuring and simplifications
– two-level minimization
– common factor extraction
– common expression resubstitution
• Trade-off between area and delay
• In commercial use for several years
– f1 = abcd+abce+ab’cd’+ab’c’d+a’c+cdf+abc’d’e’+ab’c’df’
– f2 = bdg + b’dfg + b’d’g+bd’eg
– f1 = c(a’+x)+ac’x’
– f2 = gx
– x = d(b+f) + d’(b’+e)
Lab3-9
Technology Mapping
• Translation of a technology independent
representation of a circuit into a circuit in a given
technology with optimal cost
• Optimization criteria
– minimum area
– minimum delay
– meeting specified timing constraints
– meeting specified timing constraints with minimum area
• Usages
– Technology mapping after technology independent logic
optimization
Lab3-10
Sample covers
Lab3-11
State Machine Synthesis
• Translate state table or graph
– state minimization
– state assignment to minimize the cost function
• Challenges
– state machine decomposition
– state assignment for performance
– state assignment for testability
– extract state graph from implementation
Lab3-12
Spartan II Features
 Plentiful logic and memory resources
– 15K to 200K system gates (up to 5,292 logic cells)
– Up to 57 Kb block RAM storage
 Flexible I/O interfaces
– From 86 to 284 I/Os
– 16 signal standards
 Advanced 0.25/0.22um 6-Layer Metal Process
 High performance
– System frequency as high as 200 MHz
 Advanced Clock Control with 4 Dedicated DLLs
 Unlimited Re-programmability
 Fully PCI Compliant
Lab3-13
Spartan-II Top-level Architecture
• Configurable logic blocks
– Implement logic here!
• I/O blocks
– Communicate with other
chips
– Choose from 16 signal
standards
• Block RAM
– On-chip memory for higher
performance
Lab3-14
Spartan-II Top-level Architecture
• Clocks and delay locked
loops
– Synchronize to clock on and
off chip
• Rich interconnect resources
– Three-state internal buses
• Power down mode
– Lower quiescent power
Lab3-15
CLB Slice (Simplified)
• 1 CLB holds 2 slices
• Each slice contains two sets
of the following:
– Four-input LUT
• Any 4-input logic function
• Or 16-bit x 1 RAM
• Or 16-bit shift register
Lab3-16
CLB Slice (cont’d)
• Each slice contains two sets
of the following:
– Carry & control
• Fast arithmetic logic
• Multiplier logic
• Multiplexer logic
– Storage element
• Latch or flip-flop
• Set and reset
• True or inverted inputs
• Sync. or async. control
Lab3-17
Dedicated Expansion Multiplexers
• MUXF5 combines 2 LUTs to
form
– 4x1 multiplexer CLB
Slice
– Or any 5-input function
• MUXF6 combines 2 slices to LUT MUXF6
form LUT
MUXF5
– 8x1 multiplexer
Slice
– Or any 6-input function
LUT
LUT
MUXF5
Lab3-18
I/O Block (Simplified)
• Registered input, output, 3-state control
• Programmable slew rate, pull-up, pull-down, keeper
and input delay
Lab3-19
I/O Interface Standards
• I/O can be programmed for 16 different signal
standards
– VCCO controls maximum output swing
– VREF sets input, output, three-state control
• Different banks can support different standards at the
same time
– Logic level translation
– Boards with mixed standards
Lab3-20
IOBs Organized As Independent Banks
• As many as eight banks on a
device
– Package dependent
• Each bank can be assigned
any of the 16 signal
standards
Lab3-21
High Performance Routing
• Hierarchical routing
– Singles, hexes, longs
• Sparse connections on longer
interconnects for high speed
• Routing delay depends
primarily on distance 2ns
– Direction independent
– Device-size independent
• Predictable for early design
analysis
CLB Array
Lab3-22
Power-down Mode
• Controlled by single power down pin
• All inputs blocked, appear low internally
• All outputs disabled
• All register states preserved
• Power-down status pin
• Synchronous wake up
• 100 uA typical
Lab3-23
Configuration Modes
Config. Direction of
Data Synchronizing
Mode Format Clock Use
Slave Serial FPGA receives  Processor or CPLD or another FPGA ( in Master
Serial CCLK mode) controls configuration of slave FPGA
 Also for configuring multiple slave FPGAs in a
daisy chain (2ND, 3RD FPGA, etc.).
Master Serial FPGA generates  FPGA in Master mode configures itself from a
Serial CCLK serial PROM.
 Also, 1st FPGA (master) in daisy chain controls
configuration of slave FPGA(s) in a daisy chain.
Slave Byte FPGA receives Processor or CPLD controls the fast configuration of
Parallel CCLK slave FPGA.
JTAG Serial FPGA receives Make use of existing boundary scan port
TCK
There are four ways to program a Spartan-II FPGA

Lab3-24
Spartan-II Family Overview
Device XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200

Logic Cells 432 972 1728 2700 3888 5292
Block RAM Bits 16,384 24,576 32,768 40,960 49,152 57,344
Block RAM Qty. 4 6 8 10 12 14
Max. User I/Os 86 132 176 196 260 284
Package VQ100 VQ100
CS144 CS144
TQ144 TQ144 TQ144 TQ144
PQ208 PQ208 PQ208 PQ208 PQ208
FG256 FG256 FG256 FG256
FG456 FG456 FG456
Lab3-25
Spartan-II Architecture Summary
 Delivers all the key requirements for ASIC replacement
– 200,000 gates
– 200 MHz
– Flexible I/O interfaces
– On-chip distributed and block RAM
– Clock management
– Low power
– Complete development system support
Lab3-26
Design Tools
• Standard CAE entry and verification tools
• Xilinx Implementation software implements the
design
– The design is optimized for best performance and minimal
size
– Graphical User Interface and Command Line Interface
– Easy access to other Xilinx programs
– Manages and tracks design revisions
Foundation Functional Simulation

or Alliance Design Simulator
Entry
Back Annotation
Schematic, State Mach., HDL Verification
Code, LogiBLOX, CORE Gen
Static Timing Analysis,

M1 Design Manager In-Circuit Testing
Design Implementation
Xilinx
Lab3-27
Foundation Project Manager
• Integrates all tools into one environment
Lab3-28
Schematic Entry
Lab3-29
ABEL, Verilog and VHDL Text Entry
• From schematic menu
(or via HDL Editor),
select Hierarchy -> New
Symbol Wizard… to
create symbol.
1 • Select HDL Editor &
Language Assistant to
learn by example, then
define block.
• Synthesize to EDIF.
5
4
3
2
Lab3-30
State Machine Graphical Editor
Graphical editor synthesizes into ABEL or VHDL code

Lab3-31
Simulation - Easy to Use and Learn
• Generate stimulus
easily and quickly
– Keyboard toggling
– Simple clock stimulus
– Custom formulas
• Easy debugging
– Waveform viewer
– Signals easily added and
removed
– Simulator access from
schematic
– Color-coded values on
schematic
• Script Editor
Lab3-32
What is Implementation?
• More than just “Place & Route”
• Implementation includes many phases
– Translate: Merge multiple design files into a single netlist
– Map: Group logical symbols from the netlist (gates) into
physical components (CLBs and IOBs)
– Place & Route: Place components onto the chip, connect
them, and extract timing data into reports
– Timing (Sim): Generate a back-annotated netlist for timing
simulation tools
– Configure: Generate a bitstream for device configuration
Lab3-33
Terminology
• Project
– Source file; has a defined working directory and family
• Version
– A Xilinx netlist translation of the schematic
– Multiple Versions result from iterative schematic changes
• Revision
– An implementation of a Xilinx netlist
– Multiple revisions typically result from different options
• Part type
– Specified at translation; can be changed in a new revision
Lab3-34
Starting the Flow Engine
Foundation Project Manager
Lab3-35
The Flow Engine
Implementation
phases
Implementation
status
Message area
Flow control buttons
Lab3-36
XSA-50 Board
– Xilinx XC2S50
– 7-seg LED
– 100 MHz prog. osc.
– SDRAM
• 8M*8
– Flash
• 128K bytes
– XC9572XL
– Parallel port
– PS/2 port
– VGA port
Lab3-37
Xstend Board
– 2 7-seg LED
– Bargraph LED
– Dip switch
– Pushbuttons
– Stereo Audio I/O
– RS-232
– USB 1.1
Lab3-38
Lab 4: 7-Segment Decoder
• input [3:0] sig ; // 0-F
• output [6:0] control ; // active high
a LED1 LED 2
f b a 56 48
g
b 51 27
e c
d
c 65 40
d 64 47
e 76 28
f 54 42
g 50 29
Lab3-39
4-bit Magnitude Comparator
• input [3:0] a, b ; • XSA-50 board SW1
• input agb, alb, aeb ;
• 11 input pins SW1 Pin
• XSTend Board S1 Number
S1 Pin
1 54
Number 2 64
1 30 3 63
2 58 4 56
3 74
4 75
5 66
6 77
7 80
8 79 Lab3-40
4-bit Magnitude Comparator
• output agbo, albo, aebo ;
Pin
• Use XSTend Board Number
– Bar LEDs D1 68
D2 44
D3 46
D4 49
D5 57
D6 62
D7 60
D8 67
D9 39
D10 59
Lab3-41

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Lab 4: FPGA Implementation

RTL design and

Gate Level Simulation

ASIC Layout FPGA Implementation

Always @(posedge clk) begin

There are four ways to program a Spartan-II FPGA

Device XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200

Foundation Functional Simulation

Static Timing Analysis,

Graphical editor synthesizes into ABEL or VHDL code

Flow control buttons

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