by

K. GANGADHARAN
Roll No: 11131D8106
M. Tech. in VLSI and Embedded Systems

Department of Electronics and Communication Engineering

Under the Guidance of

Smt. Ch. Phanisri, Associate Professor

GAYATRI VIDYAPARISHAD COLLEGE OF ENGINEERING (AUTONOMOUS)

VISAKHAPATNAM
August 4, 2019 CRC 1
 Abstract
• In these days microcontroller embedded systems are
widespread in a large area of products from industrial, medical,
educational to domestic domains, there are often many
modules in the designs.
For example, nearly every system includes: some intelligent
control (usually a microcontroller core), general-purpose
circuits (like LCD drivers, remote I/0 ports, RAM, EEPROM,
or data converters) and application oriented circuits for
communication interfaces and/or computation intensive task.
• So the communication between these modules is very
important and in many applications the interface is still the
bottleneck of system performance.
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Contd..
• When there is a need to implement a communication between
an integrated circuit such as a microcontroller and a set of
relatively slow peripherals, there is no point in employing any
excessively complex protocols. In this case, SPI stands among
the best candidates.
• This thesis introduces high-quality SPI Master/Slave IPs that
incorporate all necessary features required by modern
ASIC/SoC applications & shows serial data transfer between a
master and 4 slaves in all the 4 modes.
• The whole design code, is implemented in VHDL& it is
observed that maximum transfer rate is obtained when mapped
onto Xilinx Virtex5 FPGA devices.
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Main Features of SPI protocol
• Interface type : Serial (3 + N) wires
• Application : Transfer of data streams
• Transfer rate : n MHz to 10n MHz
• Transfer type : Full duplex (bidirectional data transfer)
• Time constraint : Synchronous
• Addressing : Hardware chip select

Key Features
• Serial clock with programmable polarity and phase
• User programmable baud rate
• User defined SPI word length

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 SPI Master & Slave Interaction

• MISO = Master In Slave Out

• MOSI = Master Out Slave In
• SS = Slave Select
• Sclk = Serial Clock
• HSI = Host Side Interface (internal register access)
• ITs = Interrupts
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 SPI Master architecture

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 SPI Slave architecture

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 User programmable baud rate
• The frequency of the clock is selected using spr2,spr1,spr0
• The various frequencies are generated using counter based
baud rate generator
• But more precise speed rates can be achieved using digital
frequency synthesizers

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 Clock phase & Clock polarity
• The Clock Polarity (CPOL) parameter indicates the level of the
clock signal when it is idle.
I. CPOL=0
Clock idle state is low.
II. CPOL=1
Clock idle state is high.

• The clock phase (CPHA) parameter indicates when the data should
be sampled.
I. CPHA=0
The first edge on the sclk line is used to sample the data bit
II. CPHA=1
The second edge on the sclk line is used to sample the data bit
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 Timing Diagram – Showing Clock
polarities and phases

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 Block diagram of the design
.
.
SCLK SCLK

.
MOSI MOSI
SPI Slave 1
MISO MISO
SPI Master SS
SS1
SS2
. . SCLK

.
SS3 MOSI
SS4 MISO
SPI Slave 2
SS

. . SCLK

. MOSI
MISO
SS
SPI Slave 3

SCLK
MOSI SPI Slave 4
MISO
SS
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 Simulation results of SPI Master

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 Simulation results of SPI Slave

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 Simulation results of SPI for
CPHA=0, CPOL=0

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 Simulation results of SPI for
CPHA=1, CPOL=0

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 Simulation results of SPI for
CPHA=0, CPOL=1

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 Simulation results of SPI for
CPHA=1, CPOL=1

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 Comparison of Occupied Slices

Xilinx’s FPGA device No of No of total Utilization

occupied slices
slices
Xc2s50-6tq144 185 768 24%

Xc3s500e-5fg320 184 4656 3%

Xc2v80-6cs144 184 512 35%

Xc4vlx15-12sf363 184 6144 2%

Xc5vlx30-3ff324 140 4800 2%

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 Comparison of Delays

Xilinx’s FPGA device Clock to All paths

setup paths
Xc2s50-6tq144 5.166 ns 9.305 ns

Xc3s500e-5fg320 4.014 ns 6.890 ns

Xc2v80-6cs144 2.587 ns 6.435 ns

Xc4vlx15-12sf363 1.819 ns 5.265 ns

Xc5vlx30-3ff324 1.216 ns 3.659 ns

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 Conclusion
• All the results, either for slice occupation or delays, are
obtained using the default options of the implementation
software (Xilinx ISE 9.1) with the selection of the fastest
speed grade for each FPGA device.
• From the above table, the clock to setup delay is low when
mapped onto Virte-5 device. So, a maximum transfer rate with
a utilization ratio of 2% can be obtained when mapped on to
Virte-5 FPGA device.

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 Future work
• Further improvements can be done, such as to integrate a
purely digital frequency synthesizer instead of the counter
based baud rate to allow a more precise user defined speed
rates.

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 References
[1] A.K. Oudjida, M.L. Berrandjia, A. Liacha, R. Tiar, K. Tahraoui, , “FPGA
Implementation of I2C and SPI Protocols: A Comparative Study”,
Proceedings of the 16th edition of the IEEE ICECS, pp. 507 -510,
December 13-16 2009, Yasmine Hammamet, Tunisia..
[2] A.K. Oudjida, M.L. Berrandjia, A. Liacha, R. Tiar, K. Tahraoui, Y.N
Alhoumays, “Design and test of general-purpose SPI Master/Slave IPs on
OPB bus”. 7th International Multi-Conference on Systems, Signals &
Devices,2010.
[3] Motorola Inc., “SPI Block Guide V03.06,” February 2003.
[4] F. Leens, “An Introduction to I2C and SPI Protocols,” IEEE
Instrumentation & Measurement Magazine, pp. 8-13, February 2009.
[5] Charles H. Roth, Jr. Digital Systems Design Using VHDL, PWS
Publishing Company, Bostan, 1998

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 Queries..?

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 Thank you

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