Presented By: Sunil KM

FPGA
Presented by
SUNIL KM
©2017 Graphene Semiconductor Confidential

Contents:
History of FPGA
Hardware part of FPGA
1) Basic's of FPGA
2) Difference between MPU and FPGA
3) Architecture of FPGA
4) Type's of FPGA
5) Different block's of FPGA
Softwre part of FPGA
Design Flow of FPGA:
1) Design Entry
2) Synthesis
3) Implementation
4) Bitstream Generation
5) Simulation
Applications of FPGA
Advantages of FPGA
Disadvantage of FPGA
VHDL Programming
References

Question's:
What is the FPGA
Why we are studying
Hardware of FPGA
Application of FPGA
FPGA architecture
nomenclature
XILINX FPGA technology
history of FPGA
differece between fpga and microcontroller
why we are using FPGA
advantage
disadvantage
FPGA Vender's
Types of FPGA
FPGA and JATAG
Buses inside FPGA
pre and post silicon validation
design of FPGA
FPGA and CPLD difference's
HOW to coose RTOS for FPGA.

History of FPGA
Year's Device's
1960 First MOSFET
1961 First Communication IC(SN74H4851N)
1962 First TTL
1963 First CMOS
1965 Moore’s Law
1970 PROM
1971 EPROM
1972 DST
1975 PLA
1978 PAL
1983 EEPROM
1983 GAL
1985 First FPGA
History of FPGA
It was normal for people to design on paper and transfer directly to a physical
prototype MIT Lisp Machine:

What is FPGA?
• Integrated circuit(IC's)
• The FPGA is Field Programmable Gate Array. It is a type of device that is
widely used in electronic circuits.
• FPGAs are semiconductor devices which contain programmable logic blocks
and interconnection circuits.
• using reconfigurable gate array or logic.
Field: Modifying the device function in lab/ at site where the device is installed.
Programmable:It can be programmed or reprogrammed to the required
functionality after manufacturing.
Gate: Thousand's of gate inside the FPGA chip's.
Array: All interconnection in the array form.

Why we are studing FPGA?

What is the Scope of FPGA usability ?
• Home Appliances
• Communication Systems Communication Systems
• Control Systems and Automation
• Mechanical and Civil Engineering
• Test and Measurement Industry
• Medical Equipment
• Avionics and Aerospace Application
• Academia

But we have
Microprocessor/Microcontroller
Why FPGA ?

Difference between MPU and FPGA:
FPGA Microprocessor
Perform multiple instruction at once, Only one instruction at a time Because

execution or processing is in parallel fashion execution is sequential
Serial communication operations, FPGA’s For serial communication microprocessors

are no so useful as compare to are more useful
microprocessors
FPGA’s have more power consumption Less power consumption
Higher data processing throughput Lower data processing throughput
Works on lower frequency in the range of Works on higher frequency

mega hertz
Design is expensive Cheap price

Still confusion's
??????

Example:
7 state's

7 sequential
3 parallel stages
instruction takes
takes 3sec.
7sec.

Okay
continue.....

Number of chip's inside the board:
I/O
FLASH
I/O
CPU
SDRAM
I/O
FPGA DSP
ADC
Increase the design cost and complexity.

SoC of FPGA:
Reducing the size .

Replace external device's with programmable
logic.
Reduce cost and power utilization.
CPU I/O DSP ADC

Inside of the FPGA chip:

FPGA Architecture:
configurable
pin's for
Switch programming
block's

Internal Architecture of FPGA:

Type's of FPGA:
Types of FPGAs Based on Applications
Types of FPGAs
Low End FPGAs Mid Range FPGAs High End FPGAs
low power consumption, Between the low-end and Developed for logic
low logic density and high- end FPGAs, balance density and high
low complexity per chip. between the performance performance.
Examples: and the cost. Examples:
Cyclone family from Altera, Examples: Stratix family from
Spartan family from Xilinx, Arria from Altera, Artix- Altera, Virtex family
fusion family from Microsemi 7/Kintex-7 series from from Xilinx, Speedster
etc. Xlinix etc. 22i family from Achronix
etc.

The FPGA Architecture consists of three major components
1. Programmable Logic Blocks: which implement logic functions

2. Programmable Routing (interconnects): which implements functions
3. I/O blocks: which are used to make off-chip connections

Programmable Logic Blocks or CLB:
LUT Table:
A B C D Z
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
z=(AB)'.(C+D)

A basic logic element consists of programmable combinational logic, a flip-flop, and
some fast carry logic to reduce area and delay cost.
Modern FPGAs contain a heterogeneous mixture of different blocks like dedicated

memory blocks, multiplexers. Configuration memory is used throughout the logic
blocks to control the specific function of each element.

Programmable interconnection's:
Interconnects provide direction between the logic blocks to implement the user
logic.
Pass transister
Transmission gate
Multiplexer
Programmable switch matrix
Making and breaking cross point connection.

define the function of logic block.

Programmable Routing
The programmable routing establishes a connection between logic blocks and
Input/Output blocks to complete a user-defined design unit.
There are long lines that can be used to connect critical CLBs that are physically
far from each other on the chip without inducing much delay.
It consists of multiplexers, pass transistors and tri-state buffers. Pass transistors and
multiplexers are used in a logic cluster to connect the logic elements.

• CLBs that are physically far from each other on the chip.
• Theses long lines can also be used as buses within the chip.
• Transistors are used to turn on or off connections between different lines.
• Several programmable switch matrices in the FPGA to connect these
long and short lines together in specific, flexible combinations.
• In order to connect one CLB to another CLB in a different part of the
chip often requires a connection through many transistors and switch
matrices, each of which introduces extra delay.
• It consists of multiplexers pass transistors and tri-state buffers. Pass
transistors and multiplexers are used in a logic cluster to connect the logic
elements.

Programmable I/O

IOB appears as storage elements act as either as D-FF or latch.
Mode: Synchronouse set/Reset

Asynchronouse Preset/Clear
The programmable I/O pads are used to interface the logic blocks and routing
architecture to the external components. The I/O pad and the surrounding logic circuit
form as an I/O cell.

• A Configurable input/output (I/O) Block, used to bring signals onto the chip and
send them back off again.
• It consists of an input buffer and an output buffer.
• There are pull up resistors on the outputs and sometimes pull down resistors that
can be used to terminate signals and buses.
• The polarity of the output can usually be programmed for active high or active
low output.
• There are typically flip-flops on outputs so that clocked signals can be output
directly to the pins .
• Similarly, flip-flops on the inputs reduce delay on a signal before reaching a flip-
flop, thus reducing the hold time requirement of the FPGA.

Family of FPGA:
Xilinx Specificaion
Virtex II and Spartan 3E
Xilinx all Xilinx FPGA contains
Actel CLB: Configurable logic block
Altera IOB: Input/Output Block
PI : Programmable Interconnects
RAM Block
Other Resources: Three stage buffer
global clock buffer etc.
An example of an ordering code for a Xilinx FPGA is XC4VLX60-10FFG668C. The

ordering code stands for:
XC4VLX – Family (Virtex®-4 LX)
60 – Number of system gates or logic cells (60,000 logic cells)
-10 – Speed grade (-10 speed)
FFG – Package type (Pb-free flip-chip BGA)
668 – number of pins (668 pins)
C – Temperature grade (Commercial)

FPGA Vender's
77%
23%

Where do FPGA Lies?
IC's
PLd's between ASIC

SPLD's Gate Array
CPLD's structured
ASIC
FPGA lies
Standard Cell
in between
Full Custom
• High configurable
• Fast design time
• can't support complex logic
• No reconfigurable
• Time consuming design
• expensive design
• support complex function

Why FPGA’s are not common in every product?
• FPGA is expensive because there are a lot of chips in them.
• Thousands of dollars to just have one FPGA.(contain million of logic gates,)
• not made for power optimization.
• So they are actually high power devices.
• They are volatile because they forget anything.
• friendly device then FPGA is not a friendly device because of high pins.
• So,there are a lots of disadvantages in FPGA that’s why its not so common in
every product.

Design Flow of FPGA:
FPGA Board

Five main FPGA development phases:
1) Design Entry
2) Synthesis
3) Implementation
4) Bitstream Generation
5) Simulation
Xilinx Software View

1. Design Entry:
There are 2 methods:
• Using a schematic.
• Using an HDL (Hardware Description Language).

Schematic design entry:
With schematic design entry, you draw your design on your computer using gates
and wires.
Schematic entry is nice because it documents the design in an easily readable
format.But big designs quickly become difficult to maintain, the file formats are
incompatibles between vendors, and HDLs are easier to parameterize, so many
FPGA users quickly shy away from schematic design entry.
If the designer wants to deal more with Hardware, then Schematic entry is the better
choice.

HDL design entry
Vendors used to have proprietary languages. But then came two HDL languages
(VHDL and Verilog) that quickly got popular. Now FPGA vendors support mainly
these two languages.
design is complex or the designer thinks the design in an algorithmic way then
HDL is the better choice.

2. Synthesis
Converts the input HDL source files into a netlist
Converts the input HDL source files into a netlist

• describes a list of logical FPGA elements and the
connectivity
• multiple netlists generated for complex designs
Three-step process:
• syntax check & element association
• optimisation
• technology mapping
Output files:
Xilinx format: Native Generic Circuit (.ngc)

3. Implementation
Sequence of three sub-processes:
1. Translate
2. Map
3. Place & Route (PAR)
Notice that the implement steps is actually

composed of four sub steps: Translate, Map,
Place, and Route. In the translate step, the design
is converted from a generic netlist to a Xilinx
specific netlist.

Determines the physical design layout
maps synthesised netlists (.ngc) to the target FPGA’s structure
interconnects design resources to FPGA’s internal and I/O logic.
Translate
combines all netlists and constraints into one large netlist
Xilinx format: Native Generic Database (NGD)
user-defined constraints:
pin assignment & time requirements (e.g. input clock period, maximum delay, etc.)
information provided via a User Constraints File (UCF)
Map
compares the resources specified in the input netlist (.ngd) against the
available resources of the target FPGA insufficient or incorrectly specified resources
generate errors divides netlist circuit into sub-blocks to fit into the FPGA logic
blocks

output:
Native Circuit Description (NCD, .ncd) file
Place & Route (PAR)

Place-and-route (P&R) describes several processes where the netlist elements
are physically places and mapped to the FPGA physical resources, to create a
file that can be downloaded in the FPGA chip.
iterative process, very time intensive

places physically the NCD sub-blocks into FPGA logic blocks
routes signals between logic blocks such that timing constraints are met
output:
a completely routed NCD file

4. Bitstream Generation OR Generate Programming File:
Converts the final NCD file into a format the FPGA understands
 bitstream (.bit) is the usual choice
• can be directly loaded into FPGA (e.g. via JTAG interface)
• or stored in non-volatile devices (PROMs, Flash) : downloaded to FPGA
automatically (e.g. at power-up) or upon request
 other similar choice: IEEE 1532 configuration file format (.isc)

FPGA Board

5. Simulation :
If we click the Synthesize option and perform synthesis in ISE you notice in
the console that it displays the exact command that is used to call the
executable.

Half Adder Implementation:

Half Adder:
A B SUM CARRY
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 1
Sum: AxorB
Carry: AB

Applications of FPGA
• Consumer automative.
• Test measurement and medical.
• Communication broadcast.
• Military industrial.
• computer and storage.
• They offer a powerful solution for meeting machine vision, industrial networking,
motor control and video surveillance.
• FPGAs provide a unique combination of highly parallel custom computation and
low-cost computation.

Advantages of FPGA
• The main advantages are You can do everything, you can imagine.
• They are also super-fast and some of them, even the basic FPGA have I/O
blocks are also super fast.
• High performance
• low cost
• Integration of many function
• Many available I/O standard and feature's
• Fast programming

Future of FPGA Devices
• FPGA device densities are increasing in millions of gates
• Altera’s latest device is Stratix-V
• Xilinx’s latest device is Virtex-7
• Higher density devices are expected with higher number of hard macros
FPGA are expected to stay in market for the next 50 years
• Research interests are growing more towards Coarse-grain
Reconfigurable Array (CGRA)
The unit of structure in FPGA is a LE whereas in CGRA, it is the ALU

Advantage of FPGA:
• Low cost
• supported by CAD and EDA tool's
• High density
• High speed
• Flexible
• Reusable

Disadvantage of FPGA:
The FPGA is so, much useful then why it is not at every home or in every
product because there are a lot of disadvantages of FPGAs.
 Expensive
 Use high power
 Volatile
 High pin count
 Complicated
 Many traps
 Complex tools
 Hard to choose/ compare
 HDL not easy

Verification Validation
1. Verification is a static practice of verifying documents, design, code and program. 1. Validation is a
dynamic mechanism of validating and testing the actual product.
2. It does not involve executing the code. 2. It always involves executing the code.
3. It is human based checking of documents and files. 3. It is computer based execution of
program.
4. Verification uses methods like inspections, reviews, walkthroughs, and Desk-checking etc. 4.
Validation uses methods like black box (functional) testing, gray box testing, and white box (structural)
testing etc.
5. Verification is to check whether the software conforms to specifications. 5. Validation is to check
whether software meets the customer expectations and requirements.
6. It can catch errors that validation cannot catch. It is low level exercise. 6. It can catch errors that
verification cannot catch. It is High Level Exercise.
7. Target is requirements specification, application and software architecture, high level, complete design,
and database design etc. 7. Target is actual product-a unit, a module, a bent of integrated modules, and
effective final product.
8. Verification is done by QA team to ensure that the software is as per the specifications in the SRS
document. 8. Validation is carried out with the involvement of testing team.
9. It generally comes first-done before validation. 9. It generally follows after verification.
https://www.toolsqa.com/software-testing/difference-between-verification-and-
validation/

References
https://www.elprocus.com/fpga-architecture-and-applications/
https://microcontrollerslab.com/difference-fpga-microprocessor/amp/
https://microcontrollerslab.com/fpga-introduction-block-diagram/
https://www.eetimes.com/document.asp?doc_id=1274496#
https://www.slideshare.net/abhilash128/lec-23
https://www.youtube.com/watch?v=bwoyQ_RnaiA

VHDL Programming

VHDL: VHSIC Hardware Description Language
Very High Speed Integrated Circuit.
VHDL case insensitive language.
VHDL Library
Entity Basic VHDL code
Architecture

Every piece of VHDL code is composed of at least three fundamental sections
• LIBRARY declarations: Contains a list of all libraries to be used in the design.
• ENTITY: Specifies the I/O pins of the circuit.
• ARCHITECTURE: Contains the VHDL code which describes how the circuit
should behave (function).

A LIBRARY is acollection of commonly used pieces of code. Placing such pieces inside a
library allows them to be reused or shared by other designs.
Library Declarations Library

LIBRARY ieee;
USE ieee.std_logic_1164.all ; Package
Function
Procedure
Component
Constatnt
Type

STD_LOGIC type
Value Meaning
‘U’ Uninitialized
‘X’ Forcing (Strong driven) Unknown
‘0’ Forcing (Strong driven) 0
‘1’ Forcing (Strong driven) 1
‘Z’ High Impedance
‘W’ Weak (Weakly driven) Unknown
‘L’ Weak (Weakly driven) 0.Models a pull down.
‘H’ Weak (Weakly driven) 1.Models a pull up.
‘-’ Don't Care

ENTITY
• An ENTITY is a list with specifications of all input and output pins
(PORTS) of the circuit with the following syntax.
ENTITY entity_name IS a, b
PORT ( std_logic
port_ name : signal_mode signal_type ;
port_ name : signal_mode signal_type ;
... );
END entity_name ;
IN, OUT
Example
ENTITY nand_ gate IS
PORT (a, b : IN BIT;
x : OUT BIT);
END nand_gate;

ARCHITECTURE
The ARCHITECTURE denotes the description of how the circuit should behave or
function . The syntax is as below.
ARCHITECTURE architecture_name OF
entity_name IS [declarations]
BEGIN
(code) x<=a nand b;
END architecture_name ;

VHDL Modeling Style
• Structural Style of Modeling

• Dataflow Style of Modeling
• Behavioral Style of Modeling
• Mixed Style of Modeling

Structural Style of Modeling
In the structural style of modeling, an entity is described as a set of interconnected
components. Such a model for the HALF_ADDER entity,
architecture HA_STRUCTURE of
HALF_ADDER is
component XOR
port (A, B: in BIT; SUM: out BIT);
end component;
component AND
port (A, B: in BIT; N: CARRY BIT);
entity HALF_ADDER is end component;
port (A, B: in BIT; begin
SUM, CARRY: out BIT); X1: XOR port map (A, B, SUM);
end HALF_ADDER; A1: AND port map (A, B, CARRY);
-- This is a comment line. end HA_STRUCTURE;

Example of Structural Modeling
library ieee;
use ieee.std_logic_1164.all;
ENTITY half_adder IS --- Half Adder

PORT(A,B: IN BIT std_logic ;
sum, carry_out : OUT BIT std_logic);
END half_adder;
ARCHITECTURE half_adder_beh OF half_adder IS

component and_date
port(L1,L2: IN std_logic;
C1: OUT std_logic);
end component;
component xor_date
port(L1,L2: IN std_logic;
C1: OUT std_logic);
end component;

BEGIN
u1: xor_gate port map(L1=>a, L2=>b,c1=>sum);
u2: and_gate port map(L1=>a, L2=>b,c1=>carry_out);
end structure;

Example of Dataflow Modeling:
library ieee;
ENTITY half_adder IS --- Half Adder

PORT(A,B: IN BIT ;
S, Cout : OUT BIT);
END half_adder;
ARCHITECTURE half_adder_beh OF half_adder IS

BEGIN
S <= A xor B;
Cout <= A and B;
END full_adder_beh;

Example of Behavioral Modeling:
library ieee; a b sum carry
ENTITY half_adder IS --- Half Adder 0 0 0 0
PORT(A,B: IN BIT ;
S, Cout : OUT BIT); 0 1 1 0
END half_adder;
ARCHITECTURE half_adder_beh OF half_adder IS 1 0 1 0
BEGIN
ha: process(a,b) 1 1 0 1
begin
if a='1' then
sum<=not b;
carry_out<=b;
else
sum=<=b;
carry_out<='0';
end if;
end process ha;
end behaviour;
Half Adder output:

Pre and post silicon validation /
varification

Why webug
Automatic areposition
studying ?
system(ABPS)
Chip desig complicated, bug's, signal connection wrong.
solving that bug's are difficut and time consuming.
GOAL: automatically locate bug signal on a chip in both time and space.
How to locate the bug Clustring algorithm for (BPS)
Challenging in the verification
Post-silicon validation is used to detect and fix bugs in integrated circuits and
systems after manufacture. Due to design complexity,
it is nearly impossible to detect and fix all bugs before manufacture.
Post-silicon validation is a major bottleneck in SoC design methodology.
Verification hence is also referred to as Pre-Silicon Validation (indicating activities
before the silicon chip is available) and Validation is also known as Post-Silicon
Validation.
Pre-silicon validation:
pre-silicon validation refers to the overall validation and verification
before prior to the sending the design for fabrication.
Post-silicon validation:
activity to check first few silicon before samples and making sure that the design for
mass production.
It is the last step in the developement of a semiconductor IC.
Goal is to find bugs on silicon before releasing the product.
In contrast post silicon validation occcure on actual devices running at speed in
commercial using test pattern, software logic analyzer and oscilloscope.

 Printed circuit board (PCB) are used for silicon validation.
validation process .
validation process takes lot of efforts and time. (few months) depends on the
silicon complexity.
Debugging the chip is very hard and challenging because of poor visibility of
internal signals inside the chip.
bugs fixed through multiple rounds of silicon steppings.

Skill's set required for PSV
 Soc/ ASIC architecture knowledge.
 Processer and controller knowledge
ARM
 Protocols
 low speed protocols
I2C, SPI, JTAG, UART
 High speed protocols
PCI's, USB, SATA, Ethernet
 DDR
 Bus protocols
AXI,AHB,APB

Analog IP's
SERIES, ADC/DAC, PLL, LDO
Programming skill's
strong knowledge in Embedded C
Assembly level programming
Scripting
Tcl,perl,Labview
Lab Instruments
Osscilloscope
logic analyzer
Power supply
Function generator
Validation Engineer
Protocol analyzer
 Debugging skill's
 PCB board schematics understanding

Challenges
Limited observality and controllabilty due to limited number of output pin.

Intermittend bugs
understanding complete system


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FPGA

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

Perform multiple instruction at once, Only one instruction at a time Because

Serial communication operations, FPGA’s For serial communication microprocessors

FPGA’s have more power consumption Less power consumption

Higher data processing throughput Lower data processing throughput

Works on lower frequency in the range of Works on higher frequency

Design is expensive Cheap price

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

Increase the design cost and complexity.

©2017 Graphene Semiconductor Confidential

Reducing the size .

CPU I/O DSP ADC

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

Low End FPGAs Mid Range FPGAs High End FPGAs

©2017 Graphene Semiconductor Confidential

1. Programmable Logic Blocks: which implement logic functions

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

Modern FPGAs contain a heterogeneous mixture of different blocks like dedicated

©2017 Graphene Semiconductor Confidential

Programmable switch matrix

Making and breaking cross point connection.

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

Mode: Synchronouse set/Reset

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

An example of an ordering code for a Xilinx FPGA is XC4VLX60-10FFG668C. The

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

PLd's between ASIC

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

Xilinx Software View

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

Converts the input HDL source files into a netlist

©2017 Graphene Semiconductor Confidential

Notice that the implement steps is actually

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

Place & Route (PAR)

iterative process, very time intensive