8051

MICROCONTROLLER
The necessary tools for a
Microprocessor/controller

 CPU: Central Processing Unit

 I/O: Input /Output
 Bus: Address bus & Data bus
 Memory: RAM & ROM
 Timer
 Interrupt
 Serial Port
 Parallel Port
 General-Purpose Microprocessor

 CPU for Computers

 No RAM, ROM, I/O on CPU chip itself
 Example ： Intel’s x86, Motorola’s 680x0

Many chips on mother’s board

Data Bus
CPU
General- Serial
RAM ROM I/O Timer COM
Purpose
Port Port
Micro-
processor
 Microcontroller

 A smaller computer
 On-chip RAM, ROM, I/O ports...
 Example ： Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X

CPU RAM ROM

A single chip
Serial
I/O Timer COM
Port Port

Microcontroller
 Microprocessor vs. Microcontroller
Microcontroller
Microprocessor
 CPU, RAM, ROM, I/O and timer are all
 CPU is stand-alone, RAM, ROM,
on a single chip
I/O, timer are separate
 fixed amount of on-chip ROM, RAM,
 designer can decide on the amount
I/O ports
of ROM, RAM and I/O ports.
 Microcontrollers are found in small,
 Commonly used as a CPU in
minimum component designs performing
computers
control oriented activities
 Microprocessor instruction sets are
 Microcontroller instruction sets cater to
processing intensive - Their
control of inputs and outputs - They have
instructions operate on nibbles,
instructions to set and clear individual
bytes, words, or even double words
bits and perform bit operations - They
- Addressing modes provide access
have instructions for input/output
to large arrays of data using pointers
operations, event timing, enabling and
and offsets
setting priority levels for interrupts
 Processing power is more caused by external stimuli.
 expansive  Processing power is less
 versatility  for applications in which cost, power and
 general-purpose space are critical
 single-purpose
 Embedded System

 Embedded system means the processor is embedded

into that application.
 An embedded product uses a microprocessor or
microcontroller to do one task only.
 In an embedded system, there is only one application
software that is typically burned into ROM.
 Example ： printer, keyboard, video game player
 Block Diagram

External interrupts
On-chip Timer/Counter
ROM for
Interrupt program On-chip Timer 1 Counter
Control code RAM Inputs
Timer 0

CPU

Bus Serial
4 I/O Ports
OSC Control Port

P0 P1 P2 P3 TxD RxD
Address/Data
 8051
 Today over fifty companies produce variations of the 8051.

 Several of these companies have over 50 versions of 8051.

 8051 cores are available for implementations in FPGA’s or

ASIC’s.

 The 8051 has been extremely successful, and has directly

influenced many of the more recent microcontroller
architectures.

 8051 belongs to MCS-51 family of microcontrollers

 MCS-51 was developed by Intel but other manufacturers

(e.g., Siemens, Philips) are second sources of this family.
 Features of 8051
Summary of features of the standard 8051
 8 bit CPU with registers A and B
 16 bit Program Counter (PC) and Data Pointer (DPTR)
 8 bit stack pointer
 8 bit Program Status Word (PSW)
 4K bytes internal ROM (program)
 128 bytes internal RAM (data)
– 4 register banks 00-1f
– 16 bytes (bit addressable) 20-2f
– 80 bytes of general purpose data memory 30-7f
 Four 8-bit I/O ports
 Two 16-bit timers
 Serial interface
 Control registers: TCON, TMOD, SCON, PCON, IP and IE
 2 external and 3 internal interrupt sources
 Oscillator and clock circuits
 64K external code memory space
 64K external data memory space
 210 bit-addressable locations
Comparison of the 8051 Family Members

Feature 8051 8052 8031

ROM (program space in bytes) 4K 8K 0K
RAM (bytes) 128 256 128
Timers 2 3 2
I/O pins 32 32 32
Serial port 1 1 1
Interrupt sources 6 8 6
8
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 8051
DIP
PIN
ASSIGNMENTS
 8051 Pin Descriptions
Vcc: Supply voltage.
Vss: Circuit ground.
Port 0: Port 0 is an 8-bit bidirectional I/O port. Port 0 pins that
have 1‘s written to them float, and in that state can be
used as high-impedance inputs. Port 0 is also the
multiplexed low-order address and data bus during accesses
to external Program and Data Memory.
Port 1: Port 1 is an 8-bit bidirectional I/0 port.

Port 2: Port 2 is an 8-bit bidirectional l/O port. Port 2 emits the

high-order address byte during fetches from external
Program Memory and during accesses to external Data
Memory that use 16-bit addresses (MOVX @DPTR).
 8051 Pin Descriptions
Port 3: Port 3 is an 8-bit bidirectional l/O port.

RST: Reset input. A high on this pin for two machine cycles
resets the device.
ALE/PROG: Address Latch Enable output pulse for latching
the low byte of the address during accesses to
external memory. This pin is also the program pulse
input (PROG) during programming of the EPROM
parts.
 8051 Pin Descriptions

PSEN*: Program Store Enable is the read strobe to external

Program Memory. When the device is executing code from
external Program Memory, PSEN* is activated twice each
machine cycle.
EA*/Vpp: External Access enable, EA* must be strapped to VSS in
order to enable any MCS 51 device to fetch code from
external Program memory locations starting at 0000h
upto FFFFh. EA* must be strapped to VCC for internal
program execution.
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
 8051 Oscillator and Clock
 Clock Pulses are required to synchronize all internal
operations of 8051.
 Pins XTAL1 & XTAL2 are provided to connect a resonant
circuit to form an oscillator. Typically a quartz crystal and
capacitors are employed.
 The crystal frequency is the basic internal clock frequency of
the microcontroller.
 8051 runs at typically 1 MHz to 16 MHz.
 8051 Timing
 The clock frequency, f, establishes the smallest interval of time
within the microcontroller, called the Pulse, P, time.
 The smallest interval of time to accomplish any simple
instruction, or part of a complex instruction, is the machine
cycle.
 The machine is itself made up of six states.
 A state is the basic time interval for discrete operations of the
microcontroller such as fetching an opcode byte, decoding an
opcode, executing an opcode, or writing a data byte. Two
oscillator pulses define each state.
 Programming instructions may require one, two, or four machine
cycles to be executed, depending on the type of instruction.
 The time to execute any instruction can be found by

where C is the number of cycles.

 Memory
 8051 implements a separate memory space for programs (code) and
data. Since both blocks have the same address, this is called a Harvard
architecture.

 Separating the program memory from the data memory improves

reliability since we cannot overwrite the program code and allows us to
use program ROM

 Both code and data may be internal, however, both expand using
external components to a maximum of 64K code memory and 64K data
memory.

 Internal memory consists of on-chip ROM and on-chip data RAM.

 On-chip RAM contains a rich arrangement of general purpose storage,

bit addressable storage, register banks, and special function registers.

 In the 8051, the registers and input/output ports are memory mapped
and accessible like any other memory location.

 In the 8051, the stack resides within the internal RAM, rather than in
external RAM.
 Program Memory
 Program memory normally have 4K on chip (but not in the case of 8031).
 ROM occupies code address space 0000h to 0FFFh.
 The PC is used to address code bytes from addresses 0000h to FFFFh.
 Program addresses higher than 0FFFh, which exceeds internal ROM
capacity, will cause 8051 to automatically fetch code bytes from external
program memory.
 Code can also be fetched exclusively from an external memory , addresses
0000h to FFFFh, by connecting the external access pin to gnd.
 Data Memory

 Data memory all 64K is off the chip except for a

miniscule 128 bytes.
 Internal 256 bytes is divided into two parts:
 General Purpose/Scratch Pad Memory and
 Special Function Registers.
RESET Value of Some 8051 Registers

Register Reset Value

PC 0000
ACC 0000
B 0000
PSW 0000
SP 0007
DPTR 0000
RAM are all zero.
Low Data RAM
 Bit Addressable RAM
 Individual accessing of bits is a powerful feature of microcontrollers
 Bits can be set, cleared, ANDed, ORed etc, with a single instruction
 8051 ports are bit-addressable, simplifying the interface to single bit
inputs and outputs
 The 8051 contains 210 bit-addressable locations
 128 of these locations are at addresses 20H to 2FH and the rest are
in the special function registers.
 SFRs which are bit addressable are A, B, IP, IE, TCON, SCON,
PSW, P0, P1, P2 and P3.

For example, if output lines P0.0 through P0.7 are all clear (0) and
you want to turn on the P0.0 output line you may either execute:
MOV P0,#01h || SETB 80h || SETB P0.0
Both these instructions accomplish the same thing. However, using
the SETB command will turn on the P0.0 line without effecting the
status of any of the other P0 output lines
 Special Function Registers
 Special Function Registers (SFRs) are areas of memory that control
specific functionality of the 8051 processor. SFRs are used to control the
way the 8051 functions. Each SFR has a specific purpose and format.

 For example, some SFRs

o permit access to the 8051’s 32 input/output lines.
o allows a program to read or write to the 8051’s serial port.
o allow the user to set the serial baud rate
o control and access timers, and
o configure the 8051’s interrupt system

 8051 has 21 special function registers (SFRs)

 Each SFR occupies internal RAM from 0x80 to 0xFF (but, some areas
are empty!)

 They are 8 bits wide.

 Some SFR’s are both bit-addressable and byte addressable, depending

on the instruction accessing the register
Special Function Registers
 8051 Basic Registers
The Accumulator

 The Accumulator, as it’s name suggests, is used as a

general register to accumulate the results of a large
number of instructions.

 It can hold an 8-bit (1-byte) value

 It is the most versatile register the 8051 has due to the

shear number of instructions that make use of the
accumulator.
 The ‘R’ Registers

 The ‘R’ registers are a set of eight registers that are

named R0 through R7.

 These registers are used as auxillary registers in many

operations.
ADD A, R4 ; add the value of R4 with the value of A and get the sum in A

 They are also used to temporarily store values.

MOV A,R3 ; move the value of R3 into the acc.
SUBB A,#11h ; subtract the value 11h from acc. The result is in acc.
MOV R4,A ; store the result temporarily in R4
 B Register
 B register or accumulator B at address F0H is used
along with the accumulator for multiply and divide
operations.

 MUL AB: multiplies 8 bit unsigned values in A and B and

leaves the 16 bit result in A (low byte) and B (high byte)

 DIV AB: divided A by B, leaving the integer result in A

and remainder in B.

 Aside from the MUL and DIV instructions, the ‘B’ register
is often used as yet another temporary storage register
much like a ninth ‘R’ register.

 B register is bit-addressable.
 Stack Register
 Stack pointer (SP) is an 8-bit register at address 81H

 It contains the address of the data item currently on top of the stack.

 Stack operations include pushing data on the stack and popping data off
the stack

 Pushing increments SP before writing the data

 Popping from the stack reads the data and decrements the SP

 8051 stack is kept in the internal RAM

 Depending on the initial value of the SP, stack can have different sizes

Example: MOV SP,#5FH

 On 8051 this would limit the stack to 32 bytes since the uppermost
address of on chip RAM is 7FH.
 Stack in 8051
 The default value of SP (after system reset) is 07H.

 This result in the first stack write operation to store data in

location 08H which means that register bank 1 (and possible
2 and 3) are not available.

 User may initialize the SP to avoid this.

 Program Counter (PC) and
Data Pointer (DPTR)
 8051 contains two 16-bit registers: program counter (PC) and data
pointer (DPTR). Each is used to hold address of a byte in memory.

 PC contains address of the next instruction to be executed next.

The PC is incremented automatically after every instruction byte is
fetched and may also be altered by certain instructions. The PC is
the only register that does not have an internal address.

 Data pointer (DPTR) is used to access internal and external code

and external data.

 DPTR is a 16 bit register and can be thought of two 8-bit registers:

DPL at address 82H (low byte) and DPH at address 83H (high byte)

 Example: the following instructions write 55H into external RAM

location 1000H:
MOV A,#55H
MOV DPTR,#1000H
MOVX @DPTR,A
 8051 Flag bits and the PSW register

PSW Register

CY AC F0 RS1 RS0 OV --- P

RS1 RS0 Register Bank Address

CY Carry flag
AC Auxiliary flag
0 0 0 00H-07H
F0 Available to the user for general purpose
RS1 Register Bank selector bit 1 0 1 1 08H-0FH
RS0 Register Bank selector bit 0
OV Overflow flag 1 0 2 10H-17H
--- User defined bit
P Parity flag 1 1 3 18H-1FH
 Program Status Word (PSW)
Register
 Carry flag is also the “Boolean accumulator”: 1 bit register for Boolean
instructions
Example: ANLC,25H
AND’s bit 25H with the carry flag and places the result back in the carry
flag

 Auxiliary carry flag (AC) is set if a carry was generated out of bit 3 into
bit 4 or if the result in the lower nibble is in the range 0AH to 0FH. AC is
useful in arithmetic operations on binary coded decimal (BCD) values.

 Flag 0 (F0): a general purpose flag bit available for user

 Register Bank Select Bits (RS0 and RS1): determine the active register
bank
Example: The following instructions enable register bank 3 and move
the content of R7 (address 1FH) to the accumulator
SETB RS1
SETB RS0
MOV A,R7
 Program Status Word (PSW)
Register
 Overflow flag (OV) is set after an addition or subtraction if there was an
arithmetic overflow.
o When signed numbers are added or subtracted this bit determines if the
result is in the proper range. Results greater than 127 or less than –128
will set OV bit
o When unsigned numbers are added OV can be ignored
o Example: What is the OV and the content of accumulator after the
following instruction sequence?
MOV R7, #FFH
MOV A, #0FH
ADD A,R7
o Answer: OV=0, ACC=0EH

 Parity bit (P) is automatically set or cleared in each machine cycle to

establish even parity in the accumulator
o Number of 1-bits in the accumulator plus P is always even
o P is used in serial port routines
o What is the state of P after execution of the following instruction?
MOV A,#55H
o Answer: P=0
 Addressing Modes

 The way in which the data sources and destination

addresses are specified in the instruction is called
addressing mode.

 There are eight addressing modes available in the 8051:

1. Immediate
2. Register
3. Direct
4. Indirect
5. Indexed
6. Relative
7. Absolute
8. Long
 Immediate Addressing

 The simplest way to get data to a destination is to make the

source of the data as a part of the instruction itself.
 Immediate operands are preceded by #
 Operand may be a numeric constant, a symbolic variable or an
arithmetic expression using constants, symbols and operators.
 Assembler computes the value and substitutes the immediate
data into the instruction
Example: MOV A,#12
 All instructions using immediate addressing use 8-bit data
 Exception: when initializing the data pointer, a 16-bit constant is
required
Example: MOV DPTR, #8000H
 Advantage: Immediate addressing is very fast since the value to
be loaded is included in the instruction.
 Disadvantage: Since the value to be loaded is fixed at compile-
time it is not very flexible
 Register Addressing
 Certain register names may be used as a part of
the instruction as sources or destinations of
data.

 Registers A, DPTR, and R0 to R7 may be

named as a part of the instruction.

 Other registers in 8051 may be addressed using

the direct addressing mode.

 Examples:
ADD A,R7 ; add the values of A and R7
INC DPTR ; adding 1 to the data pointer
MUL AB ; multiplying unsigned values in A & B
 Direct Addressing
 operand is specified by an 8-bit address field in the
instruction

 Examples:
ADD A,55H ; adds the values of A and contents of loc 55h
MOV P1, A ; transfers the content of acc to Port 1 (address 90H)

 Advantages:
 Direct addressing is generally fast since, although the value to be
loaded isn’t included in the instruction, it is quickly accessible since
it is stored in the 8051’s Internal RAM.
 It is also much more flexible than Immediate Addressing since the
value to be loaded is whatever is found at the given address--which
may be variable.
 Direct Addressing

 When using direct addressing any instruction which refers to an

address between 00h and 7Fh is referring to Internal Memory. Any
instrction which refers to an address between 80h and FFh is
referring to the SFR control registers that control the 8051
microcontroller itself.

 The obvious question that may arise is, "If direct addressing an
address from 80h through FFh refers to SFRs, how can I access the
upper 128 bytes of Internal RAM that are available on the 8052?“

 The answer is: You can’t access them using direct addressing. As
stated, if you directly refer to an address of 80h through FFh you will
be referring to an SFR. However, you may access the 8052’s upper
128 bytes of RAM by using the next addressing mode, "indirect
addressing."
 Register Indirect Addressing
 instruction specifies a register which contains the address of the
operand.
 Both internal and external RAM can be indirectly addressed.
 The address register for 8-bit addresses can be R0 or R1 of the
selected register bank, or the Stack Pointer.
 The address register for 16-bit addresses can only be the data
pointer register, DPTR.
 indirect addressing is represented by an @ before R0 or R1.
 Example:
MOV A, @R0 ; load the acc with the value from internal RAM which is found at
the address indicated by R0
MOVX A,@DPTR ; move the contents of the external memory address pointed to by
DPTR into the Accumulator
MOVX @DPTR,A ; write the value of the Accumulator to the external memory
address pointed to by DPTR.
 Indirect addressing always refers to Internal RAM; it never refers to
an SFR
 MOV R0,#99h ; Load the address of the serial port
MOV @R0,#01h ; Send 01 to the serial port -- WRONG!!
This is not valid
 Indexed addressing
 Indexed addressing uses a base register (either the program
counter or data pointer) and an offset (the accumulator) in
forming the effective address for a JMP or MOVC instruction.
 Only Program Memory can be accessed with indexed
addressing, and it can only be read.
 This addressing mode is intended for reading look-up tables
in Program Memory.
 A 16-bit base register (either DPTR or the Program Counter)
points to the base of the table, and the Accumulator is set up
with the table entry number. The address of the table entry in
Program Memory is formed by adding the Accumulator data to
the base pointer.
 Example:
MOVC A, @A+DPTR ; this instruction moves a byte of data from code
memory to the accumulator. The address in code
memory is found by adding the accumulator to the data
pointer
 Relative Addressing

 Relative addressing is used with certain jump instructions.

 Relative address (offset) is an 8-bit signed value (-128 to 127) which

is added to the program counter to form the address of next
instruction

 Prior to addition, the program counter is incremented to the address

following the jump (the new address is relative to the next
instruction, not the address of the jump instruction)

 This detail is of no concern to the user since the jump destinations

are usually specified as labels and the assembler determines the
relative offset

 Advantage of relative addressing: position independent codes

 Absolute Addressing

 Absolute addressing is only used with ACALL and AJMP

 The 11 least significant bits of the destination address

comes from the opcode and the upper five bits are the
current upper five bits in the program counter (PC).

 The destination is in the same 2K (211) of the source

 Long Addressing

 Long addressing is used only with the LCALL and LJMP

instructions

 These 3-bytes instructions include a full 16-bit

destination address as bytes 2 and 3

 The full 64K code space is available

 The instruction is long and position dependent

 Example:
LJMP 8AF2H ; jumps to memory location 8AF2H
 Instruction Types

8051 instructions are divided among five

groups:
1. Arithmetic
2. Logical
3. Data transfer
4. Boolean variable
5. Program branching
 ARITHMETIC INSTRUCTIONS
 8051 microcontroller has instruction to perform mathematical
calculations on data in order to alter program flow and modify
program actions.
 8051 has sufficient capability to handle the data manipulations
such as addition, subtraction, multiplication, division,
increment and decrement.
 8051 has 24 arithmetic opcodes and are grouped into the
following types:
 ARITHMETIC INSTRUCTIONS
Incrementing and Decrementing
 The simplest arithmetic operation involve incrementing or decrementing
the contents of a register Rp, or Register A, or direct and indirect
addresses.

 No math flags are affected

 All 8-bit address contents overflow from FFh to 00h
 DPTR is 16 bits; DPTR overflows from FFFFh to 0000h
 All 8-bit address contents underflows from 00h to FFh
 There is no DEC DPTR to match INC DPTR
 Arithmetic Instructions
Addition
 All addition is done with the A register as the destination of the result.
 All addressing modes may be used for the source: an immediate
number, a register, a direct address and an indirect address.
 Some instruction include the carry flag as an additional source of a
single bit that is included in the operation at the least significant bit
position.

 C flag is set to 1 if there is a carry out of bit position 7; it is cleared

otherwise
 AC flag is set to 1 if there is a carry out of bit 3; it is cleared otherwise.
 OV flag is set to 1 as per the logic expression: OV=C7 XOR C6, where
C7 and C6 are carry outs of bit position 7 and 6 respectively.
 Arithmetic Instructions
Addition with Carry

 In multi-byte arithmetic, it is necessary to add the carry flag to

higher order bytes in the addition operations.
 The instruction used for this purpose is ADDC.

 C, AC and OV flags behave exactly as they do for the ADD

commands.
 Arithmetic Instructions
Subtraction
• 8051 has commands to perform direct subtraction of two
signed, or unsigned numbers.
• Register A is the destination address for subtraction.
• All four addressing modes may be used for source addresses.
• The commands treat the carry flag as borrow and always
subtract the carry flag as a part of the operation.

• Remember to clear the carry flag to 0 if it is not to be included

as a part of the subtraction operation.
 Arithmetic Instructions
Multiplication and Division
 Multiplication and division operations use registers A and B as both
source and destination addresses for the operation.
 In multiplication operation, the unsigned number in reg A is
multiplied by unsigned number in reg B.
 In division operation, the unsigned number in reg A is divided by
unsigned number in reg B.

 In multiplication operation, the OV flag is set if A X B > FFh. Setting

the OV flag does not mean that an error has occurred. Rather, it
signals that the number is larger than 8 bits. The carry flag is always
cleared to 0.
 In division operation, the OV flag is set upon division by 0. the carry
flag is always reset.
 Arithmetic Instructions
BCD Arithmetic
 8051 provides convenience for the programmers to the decimal
number system to represent all numbers in the program.
 The opcode that adjusts the result of BCD addition is the decimal
adjust A for addition (DA A) command.

 The DA A opcode only works when used with ADD and ADDC
commands and does not give correct adjustments for SUBB, MUL
or DIV commands.
 Example: If ACC contains BCD value of 59 then:
ADD A, #1 ; adds 1 to A, leaving 5A in A register
DA A ; then adjust the result to correct BCD value 60.
Arithmetic Instructions
 Logical Instructions
 8051 logical instructions perform Boolean operations on bytes
of data on a bit-by-bit basis .

 There are also rotate opcodes that operate only on a byte, or

a byte and carry flag, to permit limited 8- and 9-bit shift
register operations.
 Logical Instructions
Byte-Level Logical Operations
 The byte-level logical operations use all the four addressing modes
(Immediate, Register, Direct and Indirect) for the source of a data
byte.
 These operations are called byte-level Boolean operations because
the entire byte is affected.
 Example:
 Logical Instructions
Byte-Level Logical Operations

 Logical operations can be performed on any byte in internal

memory without going through the accumulator
 Example:
XRL P1,#FFH ; eight bits in Port 1 are read, each bit exclusive ORed. The
result is written back to Port 1.
 Rotate instructions (RL A, RR A) shift the accumulator one bit
to the left or right. For a left rotation, MSB rolls into LSB
position. For a right rotation, LSB rolls into MSB position.
 RLC A and RRC A perform similar operations on
concatenation of carry flag and accumulator.
 SWAP A: exchanges high and low nibbles within accumulator
 Logical Instructions
Bit-Level Logical Operations
 Many of the SFRs and a unique internal RAM area is bit
addressable and may be operated upon at the individual bit level.
 Advantage: Bit operators are efficient when speed of response is
needed. Bit operators yield compact program code that
enhances program execution speed.
 Internal RAM Bit Addresses SFR Bit Addresses
Byte Bit SFR Direct Bit
Addresses Addresses address address
20 00-07 A 0E0 0E0-0E7
21 08-0F B 0F0 0F0-0F7
22 10-17 IE 0A8 0A8-0AF
23 18-1F IP 0B8 0B8-OBF
24 20-27 P0 80 80-87
25 28-2F P1 90 90-97
26 30-37 P2 0A0 0A0-0A7
27 38-3F P3 0B0 0B0-0B7
28 40-47 PSW 0D0 0D0-0D7
29 48-4F TCON 88 88-8F
2A 50-57 SCON 98 98-9F
2B 58-5F
2C 60-67
2D 68-6F
2E 70-77
2F 78-7F
Logical Instructions
Boolean (Bit) Instructions
 Data Transfers
The data transfer instruction may be divided into the
following three main types:
1. MOV destination,source
2. PUSH source or POP destination
3. XCH destination,source
The following five types of opcodes are used to move data:
4. MOV
5. MOVX
6. MOVC
7. PUSH & POP
8. XCH
Register-to-Register moves using Register Addressing
mode occur between A and R0 to R7
 Data Transfers
External Data Moves
 all external data moves must involve the A register
 MOVX is normally used with external RAM or I/O addresses.
 Data Transfers
Code Memory Read-Only Data Moves

 the data in program ROM can be accessed by using indirect

addressing and the A register in conjunction with either the PC
or DPTR.
 all data is moved from the code memory to the A register
 MOVC is normally used with internal or external ROM and can
address 4K of internal or 64K of external code.
 Data Transfers
PUSH and POP opcodes

 Stack is an area of internal RAM

 Stack Pointer (SP) register contains address of Top of the Stack
 PUSH & POP opcodes move the data between stack and specified
direct address.
 PUSH opcode copies data from source address to the stack
 POP opcode copies data from the stack to the destination address.

 When SP reaches FFh, it rolls-over to 00h (R0)

 RAM ends at address 7Fh; PUSHes above 7Fh results in errors
 Data Transfers
Data Exchanges
 Exchange instruction move data in two directions: from source
to destination and from destination to source.
 All addressing modes except immediate mode may be used in
exchange opcodes.

 Exchanges between A and any port location copy the data on

the port pins to A, while data in A is copied to the port latch.
 All exchanges are internal to 8051
 All exchanges involve register A
 When using XCHD, the upper nibble of A and the upper nibble
of the address location in Rp do not change.
 Data Transfers

Internal data RAM

 Data Transfers
External data RAM

Program ROM
 Jump and Call Instructions
 The jump and calls are decision codes that alter the flow of
the program by examining the results of the action codes and
changing the contents of the program counter.
 A jump permanently changes the contents of the PC if certain
program condition exists.
 A Call temporarily changes the contents of the PC to allow
another part of the program to run.
 Jump and Calls may also be referred as ‘branches’.
 Types of decision opcodes:
1. Jump on bit conditions
2. Compare bytes and jump if not equal
3. Decrement byte and jump if not equal
4. Jump unconditionally
5. Call a subroutine
6. Return from a subroutine
 Jump and Call Instructions
Program Range
 A jump or call instruction can replace
the contents of the PC with a new
program address that causes
program execution to begin at the
code located at the new address. The
difference, in bytes, of this new
address from the address in the
program where jump or call is located
is called the range of the jump or call.

 Jump or Call instructions may have

one of the following three ranges:
 Relative: upto PC+127 bytes, PC-128
bytes away from the PC
 Absolute Short: anywhere on a 2K
byte range
 Absolute Long: anywhere in the
program memory
 Jump and Call Instructions
Jumps
 Jump opcodes test an individual bit, or a byte, to check for
conditions that make the program jump to a new program
address.
 Jumps operate by testing for conditions that are specified in
the jump mnemonic. If the condition is true, then the jump is
taken. If the condition is false, then the instruction immediately
following the jump instruction is executed
 Bit jumps:
 Bit jumps operate according to the status of the carry flag in the PSW or
the status of any bit-addressable location.
 All bit jumps are relative to the PC
 Jump and Call Instructions
Jumps
Byte jumps:
 These are jump
instructions that tests
bytes of data
 They behave as bit
jumps.
 All byte jumps are relative
to the PC.
 CJNE doesn’t change the
contents of any register or
memory location. It can
change the CY flag to 1 if
the destination byte is
less than source byte.
 There is no zero flag; the
JZ and JNZ instructions
checks the contents of A
register for 0.
 Jump and Call Instructions
Jumps

Unconditional Jumps:
 They do not test any bit or byte to determine whether the jump
should be taken. The jump is always taken.
 These are the only jumps that can jump to any memory
location.

 JMP @A+DPTR does not change A, DPTR or any flags.

 Jump and Call Instructions
Calls and subroutines
 A Call, whether software or hardware initiated, causes a jump to the address
where the called subroutine is located.
 At the end of the subroutine, the program resumes operation at the opcode
address immediately following the call.
 Calls can be located anywhere in the program address space and can be
used many times.
 The stack area of the internal RAM is used to store the return address
 Jump Instructions
Conditional

Unconditional