William Stallings

Computer Organization
and Architecture
6th Edition
Chapter 3
System Buses

Prepared by Dr. Rusdianto

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 Computer Design
 Referred to as von Newmann Architecture (IAS computer)
 Based on 3 concepts:
 Data + Instr stored in single R/W mem
 Mem content  addressable by location
 Execution  sequential fashion

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 See p.51-52
Program Concept
 Hardwired systems are inflexible
 General purpose hardware can do different
tasks, given correct control signals
 Instead of re-wiring, supply a new set of
control signals (see Fig in next slide)

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 Fig 3.1 Hardware and Software Approach

Sequence of A&LFnc
DATA (fixed = hardwired) Results

Programming in h/w

Program= Instr codes Instr intepreter

Control signals

GP – A&L Fnc Results

DATA (Fnc depend on control signals)

Programming in s/w
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 What is a program?
 A sequence of steps
 For each step, an arithmetic or logical operation is
done
 For each operation, a different set of control
signals is needed

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 Function of Control Unit
 For each operation a unique code is provided
 e.g. ADD, MOVE
 A hardware segment accepts the code and issues
the control signals  remember fig 3.1
above.

 We have a computer!

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 Components
 The Control Unit and the Arithmetic and Logic Unit
constitute the Central Processing Unit
– Fig 3.1  CPU = instr intepreter + GP A&L Fnc
 Data and instructions need to get into the system
and results out
 Input/output (= I/O components)
 Temporary storage of code and results is needed
 Main memory = to distinguish from external storage (or
peripheral dev)

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Computer Components: Top Level View

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 See p.52
Computer Components:
Top Level View – the description
 CPU xchage data w/ memory  via registers (memory type inside CPU)
 Make use of MAR + MBR
 MAR = specifies addr in mem for next R/W
 MBR = contain data to be written into mem / rx data read from mem
 I/O AR = specifies a particular I/O dev
 I/O BR = for xchange data between I/O mod + CPU
 Memory module:
 Consist of a set of loc.=def by sequentially numberred addr
 Each loc. = a binary number intepreted as instr + data
 I/O Module:
 xfer data – external dev  CPU + Memory
 Contains internal buffer = temporarily holding data until it can be sent on

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 See p.54
Instruction Cycle
 Two steps:
 Fetch = uP read instr from mem 1 at a time
 Execute

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 Fetch Cycle – the description (see Instr Cycle)

 Program Counter (PC) holds address of next

instruction to fetch
 Processor fetches instruction from memory
location pointed to by PC
 Increment PC – always after each instr FETCH
 Unless told otherwise –e.g. = instr 100 JMP 200
 Instruction loaded into Instruction Register (IR)
 Processor interprets instruction and performs
required actions  see next slide

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 Execute Cycle – 4 actions
 Processor-memory
 data transfer between CPU and main memory
 Processor I/O
 Data transfer between CPU and I/O module
 Data processing
 Some arithmetic or logical operation on data
 Control
 Alteration of sequence of operations
 e.g. jump
 Combination of above

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 See p.55
Characteristic of Hypothetical Machine
Instr format (in bit)

0 –opcode -- 3 4 --- address --- 15 Question:

-1 word =? Bit/byte
Integer format -How many opcodes provided by this
format?
0=S 1 ---magnitude---- 15 -How many words can be addressed
directly?

 Internal CPU reg.

 PC = addr of instr
 IR = instr being exe -Describe this instr:
 AC = temp storage -0001.940
 Partial list of opcodes -0101.941
 0001 = Load AC from mem -0010.941
 0010 = Store AC to mem -write a program for (2+3)
 0101 = Add to AC from mem

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Example of Program Execution
What does the CPU do in
the FETCH cycle?
Determine in which step this
occurs?

What does the

CPU do in the EXE
cycle? Determine in
which step this
occurs?
What kind of actions does this prog.
perform?

See slide 12  4 actions in exe

cycle.

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 Instruction Cycle -
State Diagram

Involve xchange
between uP +
mem or I/O mod

Involve ONLY
internal uP ops

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 Instruction Cycle - See p.57
State Diagram –the description Memory 16-bit word
01 0 15
Instr=16bit 02 0 15

01 Memory 8-
 iac = determine the addr of next instr to be exe bit byte
02
 E.g instr = 16 bits long & Mem = organized into 16-bit words
 For next instr add 1 to the previous addr
 E.g mem=organized 8-bit byte
 For next instr  add 2 to the prev addr
 if = read instr from its mem loc into uP
 iod =analyze instr to determine type of ops to be performed + operand
to be used
 oac = if ops involve ref to operand in mem or available via I/O 
determine addr operand
 of = fetch operand from mem or read it in from I/O
 do = perform ops indicated in instr
 os = write results into mem or out to I/O

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 See p.58
Interrupts
 Mechanism by which other modules (e.g. I/O) may interrupt normal
sequence of processing  4 classes of intrpt (Table 3.1)
 Program – generated by condition occurs as a result of instr exe
 e.g. overflow, division by zero
 Timer - Generated by internal processor timer
 Used in pre-emptive multi-tasking = allow OS to perform certain Fs on a
regular basis
 I/O – generated by I/O controller, to signal
 Normal completion of ops
 A variety of error conditions
 Hardware failure – generated by a failure
 e.g. memory parity error + power failure

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Program Flow Control

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 See p.59
Program Flow Control – description Fig 3.7a
 User Prog – perform a series of WRITE calls interleaved with
processing
 Code segments 1,2,3 = sequence of instr (NOT involve I/O)
 WRITE call = I/O prog (syst utility) – perform actual I/O ops
 I/O program  3 sections
 Sec. 1 (label=4) – sequence of instr = to prepare actual I/O ops – include:
 Copying data to buffer
 Prepare parameters for dev.command
 Sec.2 – actual I/O command (without the use of intrpt)
 Command I/O issued  prog must wait for I/O dev to perform the req Fs (or
periodically poll the dev.)
 Sec.3 (label 5) – seq instr = to complete ops (setting flag indicating
success/failure)
 NOTE: I/O ops – may take long time to complete
 I/O prog = hung up (waiting for ops to complete)
 User prog = stopped at the point of WRITE call

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 See p.59
Program Flow Control – description Fig 3.7b
 Flow of control –with Intrpt – uP can be engaged in exe
other instr while I/O ops in progress
• User program  make syst call = WRITE – invoke I/O
program preparation code + actual I/O command
 After invoking I/O prog  control = return to user prog (+
external dev start rx data from mem & print it out)
 Means = I/O ops is conducted concurrently with exe instr in user
prog
 Asterisk(*) = I/O module (ext.dev) –tx intrpt_req signal to
uP (“ready to accept more data”)
 uP responds by suspending ops of current prog + branching off to
intrpt handler (prog to service that particular I/O dev)

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 See p.59
Transfer of Control via Interrupts (Fig 3.8)
from the point of view of the User program

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Instruction Cycle with Interrupts (fig 3.9)
See
p.59

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 Interrupt Cycle – description of fig 3.8 + 3.9
 Added to instruction cycle
 Processor checks for interrupt
 Indicated by an interrupt signal
 If no interrupt, fetch next instruction
 If interrupt pending:  see Fig 3.8
 Suspend execution of current program
 Save context
 Set PC to start address of interrupt handler routine
 Process interrupt
 Restore context and continue interrupted program

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 Program Timing Short I/O Wait –
Fig 3.10 = timing diagram based on flow of control (Fig 3.7)

See p.62-63

Time req for I/O ops

< time to complete WRITE ops
the exe instr Intrpt by I/O module here
between WRITE
ops

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Program Timing
Long I/O Wait
Time req for I/O ops
> time to complete
the exe instr
between WRITE
ops

Prog completed and

next WRITE begins
(but prev. WRITE not
finished = proc. wait)

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Instruction Cycle (with Interrupts) - State Diagram

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 Multiple Interrupts
 Disable interrupts
 Processor will ignore further interrupts whilst
processing one interrupt
 Interrupts remain pending and are checked after first
interrupt has been processed
 Interrupts handled in sequence as they occur
 Define priorities
 Low priority interrupts can be interrupted by higher
priority interrupts
 When higher priority interrupt has been processed,
processor returns to previous interrupt

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Multiple Interrupts - Sequential

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Multiple Interrupts – Nested

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 See p.64
Time Sequence of Multiple Interrupts

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 Connecting See p.67

 All the units must be connected

 Different type of connection for different type of unit
 Memory
 Input/Output
 CPU

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Computer Modules – Fig 3.15

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 Memory Connection – Fig 3.15a
 Receives (data is written into mem) and sends data (data is read from
mem)
 Receives addresses (of locations)
 Receives control signals
 Read
 Write
 Timing

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 Input/Output Connection(1) – Fig 3.15b

 Similar to memory from computer’s viewpoint

 Output
 Receive data from computer
 Send data to peripheral
 Input
 Receive data from peripheral
 Send data to computer

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 Input/Output Connection(2)

 Receive control signals from computer

 Send control signals to peripherals
 e.g. spin disk
 Receive addresses from computer
 e.g. port number to identify peripheral
 Send interrupt signals (control)

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 CPU Connection

 Reads instruction and data

 Writes out data (after processing)
 Sends control signals to other units
 Receives (& acts on) interrupts

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 Buses
 There are a number of possible interconnection systems
 Single and multiple BUS structures are most common
 e.g. Control/Address/Data bus (PC)
 e.g. Unibus (DEC-PDP)

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 What is a Bus?

 A communication pathway connecting two or more devices

 Usually broadcast
 Often grouped
 A number of channels in one bus
 e.g. 32 bit data bus is 32 separate single bit channels
 Power lines may not be shown

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 Data Bus
 Carries data
 Remember that there is no difference between
“data” and “instruction” at this level
 Width is a key determinant of performance
 8, 16, 32, 64 bit
 More bits  higher performance
 How many bits does Intel i7 have?

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 Address bus
 Identify the source or destination of data
 e.g. CPU needs to read an instruction (data) from a given location in
memory
 Bus width determines maximum memory capacity of system
 e.g. 8080 has 16 bit address bus giving 64k address space
 How many address space does Intel i7 provide?
 What happens if we set up a hard-disk with the address space
bigger than that of maximum address space allowed? (provide
example!)

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 Control Bus
 Control and timing information
 Memory read/write signal
 Interrupt request
 Clock signals

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Bus Interconnection Scheme

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 Big and Yellow?
 What do buses look like?
 Parallel lines on circuit boards
 Ribbon cables
 Strip connectors on mother boards
 e.g. PCI
 SATA (new product of processor….dual-core, i7 etc)
 Sets of wires
 SATA (only seven conductors instead of 40 or 80)
 Slide 51 …..more on SATA

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 Single Bus Problems
 Lots of devices on one bus leads to:
 Propagation delays
 Long data paths mean that co-ordination of bus use
can adversely affect performance
 If aggregate data transfer approaches bus capacity
 Most systems use multiple buses to overcome these problems

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Traditional (ISA) (with cache)

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High Performance Bus

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 Bus Types

 Dedicated
 Separate data & address lines
 Multiplexed
 Shared lines
 Address valid or data valid control line
 Advantage - fewer lines
 Disadvantages
 More complex control
 Ultimate performance

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 Bus Arbitration

 More than one module controlling the bus

 e.g. CPU and DMA controller
 Only one module may control bus at one time
 Arbitration may be centralised or distributed

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 Centralised Arbitration

 Single hardware device controlling bus access

 Bus Controller
 Arbiter
 May be part of CPU or separate

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 Distributed Arbitration

 Each module may claim the bus

 Control logic on all modules

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 PCI Bus

 Peripheral Component Interconnection (PCI)

 Intel released to public domain
 32 or 64 bit
 50 lines (ribbon cable)
 SATA (Serial Advanced Technology Attachment), is
 an IDE (Integrated Drive Electronics) standard first released in
2001 for connecting devices like optical drives and hard drives to
the motherboard.
 seven conductors instead of 50

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 Foreground Reading

 Stallings, chapter 3 (all of it)

 www.pcguide.com/ref/mbsys/buses/

 In fact, read the whole site!

 www.pcguide.com/

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