CMOS Inverter: © Digital Integrated Circuits Inverter

CMOS Inverter
N Well VDD
VDD PMOS 2l
Contacts
PMOS
In Out
In Out
Metal 1
Polysilicon
NMOS
NMOS
GND
© Digital Integrated Circuits2nd Inverter

Two Inverters
Share power and ground
Abut cells
VDD
Connect in Metal

CMOS Inverter
First-Order DC Analysis
V DD V DD
Rp
VOL = 0
VOH = VDD
V out VM = f(Rn, Rp)
V out
Rn
V in 5 V DD V in 5 0

CMOS Inverter: Transient Response
V DD V DD
Rp tpHL = f(R on.CL)

= 0.69 RonCL
V out
V out
CL
CL
Rn
V in 5 0 V in 5 V DD
(a) Low-to-high (b) High-to-low

Voltage Transfer
Characteristic

PMOS Load Lines
IDn
V in = V DD +VGSp
IDn = - IDp
V out = VDD +VDSp
V out
IDp IDn IDn

Vin=0 Vin=0
Vin=1.5 Vin=1.5
V DSp V DSp Vout

VGSp=-1
VGSp=-2.5
Vin = V DD+VGSp Vout = V DD+VDSp
IDn = - IDp

CMOS Inverter Load Characteristics
ID n
Vin = 0 Vin = 2.5
PMOS Vin = 0.5 Vin = 2 NMOS
Vin = 1 Vin = 1.5

Vin = 1.5 Vin = 1
Vin = 1.5 Vin = 1

Vin = 2 Vin = 0.5
Vin = 2.5 Vin = 0
Vout

CMOS Inverter VTC
Vout
NMOS off
2.5 PMOS res
NMOS s at
PMOS res
2
NMOS sat
1.5
PMOS sat
1
NMOS res
PMOS sat NMOS res
0.5
PMOS off
0.5 1 1.5 2 2.5 Vin

Switching Threshold as a function
of Transistor Ratio
1.8
1.7
1.6
1.5
1.4
V (V)
1.3
M
1.2
1.1
0.9
0.8
0 1
10 10
W /W
p n
Determining VIH and VIL
Vout
V OH
VM
V in
V OL
V IL V IH
A simplified approach

Inverter Gain
0
-2
-4
-6
-8
gain
-10
-12
-14
-16
-18
0 0.5 1 1.5 2 2.5
V (V)
in

Gain as a function of VDD
2.5 0.2
2
0.15
1.5
Vout (V)
Vout(V)
0.1
0.05
0.5
Gain=-1
0
0 0 0.05 0.1 0.15 0.2
0 0.5 1 1.5 2 2.5 V (V)
V (V) in
in

Simulated VTC
2.5
1.5
Vout(V)
0.5
0
0 0.5 1 1.5 2 2.5
V (V)
in

Impact of Process Variations
2.5
2
Good PMOS
Bad NMOS
1.5
Vout(V)
Nominal
1
Good NMOS
Bad PMOS
0.5
0
0 0.5 1 1.5 2 2.5
Vin (V)

Propagation Delay

CMOS Inverter Propagation Delay
Approach 1
VDD
tpHL = CL Vswing/2
Iav
Vout CL
~
Iav CL kn VDD
Vin = V DD

CMOS Inverter Propagation Delay
Approach 2
VDD
tpHL = f(Ron.CL)
= 0.69 RonCL
Vout
Vout ln(0.5)
CL
1 VDD
Ron
0.5
0.36
Vin = V DD
t
RonCL

CMOS Inverters
VDD
PMOS
1.2mm
=2l
Out
In
Metal1
Polysilicon
NMOS
GND

Transient Response
3
2.5
?
2
tp = 0.69 CL (Reqn+Reqp)/2
1.5
Vout(V)
tpHL tpLH
1
0.5
-0.5
0 0.5 1 1.5 2 2.5
t (sec) -10
x 10

Design for Performance
 Keep capacitances small

 Increase transistor sizes
 watch out for self-loading!
 Increase VDD (????)

Delay as a function of VDD
5.5
4.5
4
tp(normalized)
3.5
2.5
1.5
1
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
V (V)
DD
Device Sizing
-11
x 10
3.8
3.6 (for fixed load)
3.4
3.2
tp(sec)
2.8 Self-loading effect:

2.6 Intrinsic capacitances
dominate
2.4
2.2
2
2 4 6 8 10 12 14
S

NMOS/PMOS ratio
-11
x 10
5
tpLH tpHL
4.5
tp b = Wp/Wn
tp(sec)
3.5
3
1 1.5 2 2.5 3 3.5 4 4.5 5
b

Impact of Rise Time on Delay
0.35
0.3
tpHL(nsec)
0.25
0.2
0.15
0 0.2 0.4 0.6 0.8 1
trise (nsec)

Inverter Sizing

Inverter Chain
In Out
CL
If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?
May need some additional constraints.

Inverter Delay
• Minimum length devices, L=0.25mm
• Assume that for WP = 2WN =2W 2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays
W
• Analyze as an RC network
1 1
 WP   WN 
RP  Runit    Runit    RN  RW
 Wunit   Wunit 
Delay (D): tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL
W
Load for the next stage: C gin  3 Cunit
Wunit
Inverter with Load
Delay
RW
CL
RW Load (CL)
tp = k RWCL
k is a constant, equal to 0.69

Assumptions: no load -> zero delay
Wunit = 1
Inverter with Load
CP = 2Cunit Delay
2W
W
Cint CL
Load
CN = Cunit
Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)

= Delay (Internal) + Delay (Load)

Delay Formula
Delay ~ RW Cint  C L 
t p  kRW Cint 1  C L / Cint   t p 0 1  f /  
Cint = Cgin with   1

f = CL/Cgin - effective fanout
R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit

Apply to Inverter Chain
In Out
1 2 N CL
tp = tp1 + tp2 + …+ tpN

 C gin, j 1 
t pj ~ RunitCunit 1  
 C 
 gin, j 
N N  C gin, j 1 
t p   t p , j  t p 0  1  , C gin, N 1  C L
 C
i 1 

j 1 gin, j 

Optimal Tapering for Given N
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N
Minimize the delay, find N - 1 partial derivatives
Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1
Size of each stage is the geometric mean of two neighbors

C gin, j  C gin, j 1C gin, j 1
- each stage has the same effective fanout (Cout/Cin)
- each stage has the same delay

Optimum Delay and Number of
Stages
When each stage is sized by f and has same eff. fanout f:
f N  F  CL / Cgin,1
Effective fanout of each stage:
f NF
Minimum path delay

t p  Nt p 0 1  N F /  
Example
In Out
1 f f2 CL= 8 C1
C1
CL/C1 has to be evenly distributed across N = 3 stages:
f 38 2

Optimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
ln F
CL  F  Cin  f Cin with N 
N
ln f
t p 0 ln F  f  

t p  Nt p 0 F /   1 1/ N
  
  ln f ln f


t p t p 0 ln F ln f  1   f
  0
f  ln f 2
For  = 0, f = e, N = lnF f  exp 1   f 

Optimum Effective Fanout f
Optimum f for given process defined by 
f  exp 1   f 
fopt = 3.6
for =1

Impact of Self-Loading on tp
No Self-Loading, =0 With Self-Loading =1
60.0
40.0
u/ln(u)
x=10,000
x=1000
20.0 x=100
x=10
0.0
1.0 3.0 5.0 7.0
u

Normalized delay function of F

t p  Nt p 0 1  N F /  

Buffer Design
N f tp
1 64 1 64 65
1 8 64
2 8 18
1 4 16 64 3 4 15
1 64 4 2.8 15.3
2.8 8 22.6

Power Dissipation

Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents

Short Circuit Path between Supply Rails during Switching
• Leakage
Leaking diodes and transistors

Dynamic Power Dissipation
Vdd
Vin Vout
CL
Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f
Not a function of transistor sizes!

Need to reduce CL, Vdd, and f to reduce power.

Modification for Circuits with Reduced Swing
Vdd
Vdd
Vdd -Vt
CL
E 0  1 = CL  Vdd   Vdd – Vt 
Can exploit reduced sw ing to low er power

(e.g., reduced bit-line swing in memory)

Adiabatic Charging
2 2

Adiabatic Charging

Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
E N = CL  V dd2  n N 
EN : the energy consumed for N clock cycles

n(N ): the number of 0->1 transition in N clock cycles
EN n N  2
P = lim --------  f =  lim ------------  C V  f clk
avg N   N clk N   N  L dd
n N 
0  1 = lim ------------
N N
P avg = 0 1  C  Vdd 2  f clk

 L

Transistor Sizing for Minimum
Energy In Out
Cext
Cg1 1 f
 Goal: Minimize Energy of whole circuit

 Design parameters: f and VDD
 tp  tpref of circuit with f=1 and VDD =Vref
 f  F 
t p  t p 0  1    1   
    f  
VDD
t p0 
VDD  VTE

Transistor Sizing (2)
 Performance Constraint (=1)
 F  F
 2  f    2  f  
tp t p0  f  VDD Vref  VTE  f 
  1
t pref t p 0 ref 3  F  Vref VDD  VTE 3  F 
 Energy for single Transition
E  VDD
2
C g1 1   1  f   F 
2
E  VDD   2  2 f  F 
   
 
Eref  Vref   4  F 

Transistor Sizing (3)
VDD=f(f) E/Eref=f(f)
4 1.5
3.5
F=1
3
normalized energy
2 1
2.5
vdd (V)
2 5
1.5
0.5
1
10
0.5 20
0 0
1 2 3 4 5 6 7 1 2 3 4 5 6 7
f f

Short Circuit Currents
Vd d
Vin Vout
CL
0.15
0.10
IVDD (mA)
0.05
0.0 1.0 2.0 3.0 4.0 5.0

Vin (V)

How to keep Short-Circuit Currents Low?
Short circuit current goes to zero if tfall >> trise,

but can’t do this for cascade logic, so ...
Minimizing Short-Circuit Power
8
Pnorm
5
Vdd =3.3
4
Vdd =2.5
3
1
Vdd =1.5
0
0 1 2 3 4 5
t /t
sin sout

Leakage
Vd d
Vout
Drain Junction
Leakage
Sub-Threshold
Current
Sub-threshold current one of most compelling issues

Sub-Threshold
in low-energy circuitCurrent
design!Dominant Factor

Reverse-Biased Diode Leakage
GATE
p+ p+
N
Reverse Leakage Current

+
V
- dd
IDL = JS  A
2
JS = JS
1-5pA/ mmpA/mm2
= 10-100 for a 1.2 mm
at 25 degCMOS technology
C for 0.25mm CMOS
JS doubles for every 9 deg C!
Js double with every 9oC increase in temperature

Subthreshold Leakage Component

Static Power Consumption
Vd d
Istat
Vout
CL
Vin =5V
Pstat = P(In=1).Vdd . Istat
Wasted •energy … over dynamic consumption

Dominates
Should be avoided in almost all cases,
• Not a function of switching frequency
but could help reducing energy in others (e.g. sense amps)

Principles for Power Reduction
 Prime choice: Reduce voltage!
 Recent years have seen an acceleration in
supply voltage reduction
 Design at very low voltages still open
question (0.6 … 0.9 V by 2010!)
 Reduce switching activity
 Reduce physical capacitance
 Device Sizing: for F=20
– fopt(energy)=3.53, fopt(performance)=4.47

Impact of
Technology
Scaling

Goals of Technology Scaling
 Make things cheaper:

 Want to sell more functions (transistors)
per chip for the same money
 Build same products cheaper, sell the
same part for less money
 Price of a transistor has to be reduced
 But also want to be faster, smaller,
lower power

Technology Scaling
 Goals of scaling the dimensions by 30%:

 Reduce gate delay by 30% (increase operating
frequency by 43%)
 Double transistor density
 Reduce energy per transition by 65% (50% power
savings @ 43% increase in frequency
 Die size used to increase by 14% per
generation
 Technology generation spans 2-3 years

Technology Generations

Technology Evolution (2000 data)
International Technology Roadmap for Semiconductors

Year of
1999 2000 2001 2004 2008 2011 2014
Introduction
Technology node
180 130 90 60 40 30
[nm]
Supply [V] 1.5-1.8 1.5-1.8 1.2-1.5 0.9-1.2 0.6-0.9 0.5-0.6 0.3-0.6
Wiring levels 6-7 6-7 7 8 9 9-10 10
Max frequency 14.9
1.2 1.6-1.4 2.1-1.6 3.5-2 7.1-2.5 11-3
[GHz],Local-Global -3.6
Max mP power [W] 90 106 130 160 171 177 186
Bat. power [W] 1.4 1.7 2.0 2.4 2.1 2.3 2.5
Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

Technology Evolution (2003 data)
International Technology Roadmap for Semiconductors

Year of
2003 2004 2007 2010 2013 2016 2018
Introduction
Technology node
90 65 45 32 22
[nm]
Supply [V] 1.0-1.2 0.9-1.2 0.8-1.1 0.7-1.0 0.6-0.9 0.5-0.8 0.5-0.7
Wiring levels 9-13 10-14 11-15 12-16 12-16 14-18 14-18
Max frequency 4.17/ 9.28/ 15/ 22.98/ 39.68/ 53/
2.9/2
[GHz],Local-Global 2.5 4.88 9.5 18.6 36.37 56.8
Max mP power [W] 149/80 158/84 189/104 218/120 251/138 288/158 300/168
Bat. power [W] 2.1 2.2 2.5 2.8 3.0 3.0 3.0
Node years: 2007/65nm, 2010/45nm, 2013/32nm, 2016/22nm

Technology Evolution (1999)

ITRS Technology Roadmap
Acceleration Continues

Technology Scaling (1)
2
10
Minimum Feature Size (micron)
1
10
0
10
-1
10
-2
10
1960 1970 1980 1990 2000 2010
Year
Minimum Feature Size

Number of components per chip

tp decreases by 13%/year
50% every 5 years!
Propagation Delay

rs

ea
100 x1.4 / 3 y 1000
0.7
Power Dissipation (W)
Power Density (mW/mm2 )

ears

y
3
10 / 3
x4

100
10
0.1
MPU
DSP
0.01 1
1 10
80 85 90 95 Scaling Factor 
Year （normalized by 4 mm design rule ）
(a) Power dissipation vs. year. (b) Power density vs. scaling factor.
From Kuroda
Technology Scaling Models
• Full Scaling (Constant Electrical Field)

ideal model — dimensions and voltage scale
together by the same factor S
• Fixed Voltage Scaling

most common model until recently —
only dimensions scale, voltages remain constant
• General Scaling
most realistic for todays situation —
voltages and dimensions scale with different factors

Scaling Relationships for Long Channel Devices

Transistor Scaling
(velocity-saturated devices)

mProcessor Scaling
P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001

mProcessor Power

mProcessor Performance

2010 Outlook
 Performance 2X/16 months
 1 TIP (tera instructions/s)
 30 GHz clock
 Size
 No of transistors: 2 Billion
 Die: 40*40 mm
 Power
 10kW!!
 Leakage: 1/3 active Power

Some interesting questions
 What will cause this model to break?

 When will it break?
 Will the model gradually slow down?
 Power and power density
 Leakage
 Process Variation

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CMOS Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

Rp tpHL = f(R on.CL)

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

IDp IDn IDn

V DSp V DSp Vout

© Digital Integrated Circuits2nd Inverter

PMOS Vin = 0.5 Vin = 2 NMOS

Vin = 1 Vin = 1.5

Vin = 1.5 Vin = 1

Vin = 2.5 Vin = 0

© Digital Integrated Circuits2nd Inverter

0.5 1 1.5 2 2.5 Vin

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

 Keep capacitances small

© Digital Integrated Circuits2nd Inverter

3.6 (for fixed load)

2.8 Self-loading effect:

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

May need some additional constraints.

© Digital Integrated Circuits2nd Inverter

k is a constant, equal to 0.69

Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)

© Digital Integrated Circuits2nd Inverter

t p  kRW Cint 1  C L / Cint   t p 0 1  f /  

Cint = Cgin with   1

© Digital Integrated Circuits2nd Inverter

tp = tp1 + tp2 + …+ tpN

© Digital Integrated Circuits2nd Inverter

Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N

Minimize the delay, find N - 1 partial derivatives

Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1

Size of each stage is the geometric mean of two neighbors

© Digital Integrated Circuits2nd Inverter

Effective fanout of each stage:

CL/C1 has to be evenly distributed across N = 3 stages:

© Digital Integrated Circuits2nd Inverter

For  = 0, f = e, N = lnF f  exp 1   f 

© Digital Integrated Circuits2nd Inverter

No Self-Loading, =0 With Self-Loading =1

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

• Short Circuit Currents

© Digital Integrated Circuits2nd Inverter

Power = Energy/transition * f = CL * Vdd2 * f

Not a function of transistor sizes!