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Bruce Zhang
20170605
content
1. Power up sequence
2. First rate change context
3. Mission mode flow
4. Power gating flow
5. Slicer rotation reset
6. IQ recovery
7. FW usage limitation
No
Clean dac overide/IQ/RX_OVRD/TX_OVRD Yes
Check mpll
Yes
MPLL RECAL function
recal
Check RTN reset
No
Yes Check rx No
Check pma tx
Startup offset calibration / Power gating reset ack assertion
No Yes
No Check RX
RESET IRQ No
with Override Check pma tx
protection rate change /
mpll recal
Yes
Generate RX reset
Yes
Check TX No
RESET IRQ
with Override
protection Update tx DCC TX DCC recal function
Yes
No
Check rx
reset IRQ Clean tx req IRQ
Yes
Check No
pma_rx_ack Check rx req
de-assertion
Yes
Check TX
REQ IRQ
Yes Mission mode
Yes
Check RX
© 2015 Synopsys, Inc. 4 REQ IRQ
Power up sequence
• FW does RTUNE calibration
o ESM25 does 8 rounds of RTUNE calibration, each round of RTUNE result is
stored into AON registers and these value is used for restore during power gating.
Master configure
yes
dfe
go to P0 with FULL rate no
run the RX TERMINATION calibration FSM RX DCC CAL: differential, common mode
BIN: RX_DCC_B_DF, RX_CAL_DCC
BIN: RX_DCC_B_CM_P, RX_CAL_DCC
LIN: RX_DCC_B_DF, RX_CAL_DCC
calibrate AFE offset: ATT, CTLE, VGA LIN: RX_DCC_B_CM_P, RX_CAL_DCC
ATT_OFF, CAL_AFE
CTLE_OFF, CAL_AFE
VGA_OFF, CAL_AFE
phase slicer offset calibration
SL_PE, CAL_PE, binary search
slicer setup calibration SL_PO, CAL_PO, binary search
SETUP_SLC_VGA, CAL_AFE, binary search
Store RX DCC and IQC result into AON MPLLA TX DCC full rate and half rate:
differential, common mode
BIN: TX_DCC_DF, TX_CAL_DCC
BIN: TX_DCC_CM_P, TX_CAL_DCC
LIN: TX_DCC_DF, TX_CAL_DCC
LIN: TX_DCC_CM_P, TX_CAL_DCC
Change RX clock to half rate MPLLB TX DCC full rate and half rate:
differential, common mode
BIN: TX_DCC_DF, TX_CAL_DCC
BIN: TX_DCC_CM_P, TX_CAL_DCC
LIN: TX_DCC_DF, TX_CAL_DCC
LIN: TX_DCC_CM_P, TX_CAL_DCC
end calibration
© 2015 Synopsys, Inc. 7
First rate change context
• First rate change context is based on bank solution.
• Each of TX and RX has 4 banks. Each bank has its own clock setup solution
and DCC solution.
• In RX side, based on bank solution, each bank stores phase dcc, data dcc or
bypass dcc and IQC. All of these calibration need to be done in both full rate
and half rate.
• After first rate change, in any time of rate change or bank switching, FW does
not do calibration again. FW restores DCC, IQC result into analog based on
bank selection and RX rate.
MPLLA_TUNE_VAL
mpllb_done tx_vco_a_bank_0
check mpllb MPLLB_TX_DCC_FULL_DIFF
done MPLLB_TX_DCC_FULL_CM
MPLLB_TX_DCC_HALF_DIFF
MPLLB_TX_DCC_HALF_CM
MPLLB_TX_DCC_DONE
N
Y
MPLLB_BANK_0 Does mplllb TX tx_vco_a_bank_1
MPLLB_DONE DCC MPLLB_TX_DCC_FULL_DIFF
MPLLB_TX_DCC_FULL_CM
MPLLB_TX_DCC_HALF_DIFF
MPLLB_TUNE_VAL MPLLB_TX_DCC_HALF_CM
MPLLB_TX_DCC_DONE
Update mpllb TX
MPLLB_BANK_1 DCC tx_vco_a_bank_2
MPLLB_TX_DCC_FULL_DIFF
MPLLB_TX_DCC_FULL_CM
MPLLB_DONE MPLLB_TX_DCC_HALF_DIFF
MPLLB_TX_DCC_HALF_CM
MPLLB_TUNE_VAL remove mpll mpllb_recal_bank_sel
MPLLB_TX_DCC_DONE
recal interrupt
MPLLB_BANK_2 tx_vco_a_bank_3
mpllb_recal_bank_sel MPLLB_TX_DCC_FULL_DIFF
MPLLB_TX_DCC_FULL_CM
MPLLB_DONE MPLLB_TX_DCC_HALF_DIFF
MPLLB_TX_DCC_HALF_CM
MPLLB_TUNE_VAL MPLLB_TX_DCC_DONE
MPLLB_TUNE_VAL
set pma TX DCC in rate change
rx_vco_bank_0
RX_CAL_RX_DCC_FULL_DIFF
RX_CAL_RX_DCC_FULL_CM
RX_CAL_RX_DCC_FULL_PHASE_DIFF
RX_CAL_RX_DCC_FULL_PHASE_CM rx reset or rx rate
RX_CAL_IQ_FULL
change
RX_CAL_RX_DCC_HALF_DIFF
RX_CAL_RX_DCC_HALF_CM
RX_CAL_RX_DCC_HALF_PHASE_DIFF
RX_CAL_RX_DCC_HALF_PHASE_CM
RX_CAL_IQ_HALF
check VCO done
VCO_DONE
rx_vco_bank_1 N
RX_CAL_RX_DCC_FULL_DIFF
RX_CAL_RX_DCC_FULL_CM
RX_CAL_RX_DCC_FULL_PHASE_DIFF do RX DCC Y
RX_CAL_RX_DCC_FULL_PHASE_CM rx_vco_bank_sel
RX_CAL_IQ_FULL
RX_CAL_RX_DCC_HALF_DIFF
RX_CAL_RX_DCC_HALF_CM
RX_CAL_RX_DCC_HALF_PHASE_DIFF
RX_CAL_RX_DCC_HALF_PHASE_CM
RX_CAL_IQ_HALF
VCO_DONE update RX DCC
rx_vco_bank_2
RX_CAL_RX_DCC_FULL_DIFF
RX_CAL_RX_DCC_FULL_CM
RX_CAL_RX_DCC_FULL_PHASE_DIFF
RX_CAL_RX_DCC_FULL_PHASE_CM
RX_CAL_IQ_HALF
RX_CAL_RX_DCC_HALF_DIFF
clean IRQ
RX_CAL_RX_DCC_HALF_CM
RX_CAL_RX_DCC_HALF_PHASE_DIFF
RX_CAL_RX_DCC_HALF_PHASE_CM
RX_CAL_IQ_HALF
VCO_DONE
rx_vco_bank_3
RX_CAL_RX_DCC_FULL_DIFF
RX_CAL_RX_DCC_FULL_CM
RX_CAL_RX_DCC_FULL_PHASE_DIFF
RX_CAL_RX_DCC_FULL_PHASE_CM
RX_CAL_RX_DCC_HALF_DIFF
RX_CAL_RX_DCC_HALF_CM
RX_CAL_RX_DCC_HALF_PHASE_DIFF
RX_CAL_RX_DCC_HALF_PHASE_CM
set RX DCC in rate change
VCO_DONE
• For fast of RX DCC, TX DCC and AFE calibration from rate change, fast loop
part is added in the beginning of mission mode
o Each round of fast loop, one code is updated for RX DCC and TX DCC
and AFE calibration.
o In first 100 loops, RX DCC and TX DCC is update to a stable state.
mm
Enable IRQ
mpll_recal/rx_reset/rx_req/
rx_adapt/tx_reset/tx_req
N
First_DCC_LOOP=0
wait 1s
MM_RX_DCC==0
RX_DCC
Y
MM_TX_DCC==0
TX_DCC
Y
MM_AFEOC_en==0
N
First_DCC_LOOP=0
Y
MM_PSOC_en==0
Y
MM_DSOC_en==0
Y
MM_DFE_en==0
N
© 2015 Synopsys, Inc. 12 mission mode DFE adaptation
Power gating flow
• FW and RTL restore analog parameters after Power Gating for quick power up
o AFE offset
o Slicer offset
o DCC offset
o IQ offset
o VGEN offset
o SIGDET offset
o MPLL tune code
o RTUNE code
o adaptation code
powerdown P1 P1.2 P1
vgen_calib
copy
copy rx_dcc_calib
copy tx_dcc_calib
iq calib
copy offset_calib
data calib
copy mplla_calib
aon bypass calib
copy mpllb_calib
adapt code
copy rtune_calib
copy sigdet_calib
pg_reset
phystatus
• RX to TX Loopback timing
o During RX to TX loopback function, TX clock path is switched to RX clock
path for loopback function.
o FW redoes TX DCC for new clock path. It takes 100us to finish TX DCC
and internal power state transition.
o When disabling RX to TX loopback function, FW needs 50us for TX DCC
restore and internal power state transition.