Sequential Circuits

Sequential Circuits are those whose output is dependent not only on the
state of present input signals but also on the past output.
Such circuits employ storage (memory) elements, in the feedback path, to
hold the past state of outputs. Thus, the circuit behavior is specified by a
time sequence of inputs and internal states.
 Sequential Circuits
Sequential circuit has Combinational circuit (shown below) such that it:-
accepts digital signals from external inputs and from outputs of memory
elements (flip flop).
generates signals for external outputs and for inputs to memory elements,
referred to as Excitation.
In Sequential circuits, synchronization is achieved by an external timing
device called Clock generator.
 Sequential Circuits
Storage Element
 A Storage Element or a Memory element is a medium in which
one bit of information (0 or 1) can be stored or retained until
necessary, and thereafter its contents can be replaced by a new
value.
 The contents of memory elements can be changed by the
outputs of combinational circuits that are connected to its input.
 Time delay devices are also used as Storage elements in
sequential circuits as their internal propagation delay is
sufficient to produce the needed effect of memory/storage
element
 Flip-flops are also employed as memory storage elements in
sequential circuits.
 Sequential Circuits
Types of Sequential Circuits-
Synchronous Seq Circuits Asynchronous Seq Circuits
Synchronous Seq Circuits:
A circuit whose behavior can be defined from the knowledge of its signal at
discrete instants of time is referred to as a synchronous sequential circuit.
In these circuits:-
Synchronization is achieved by a timing device known as a system clock,
which generates a periodic train of clock pulses as shown below.
Outputs are affected only with the application of a clock pulse. The rate of
clock pulses must be slow enough to permit the slowest circuit to respond.
This limits the speed of all circuits.

Memory elements are affected only at discrete instants of time.

Synchronous circuits are stable and their timing can be easily broken down
into independent discrete steps, each of which can be considered separately.
 Sequential Circuits
Asynchronous Seq Circuits:
 A sequential circuit, whose behavior depends upon the sequence in
which the input signals change, is referred to as an asynchronous
sequential circuit.
 Output is affected whenever the input changes.
 Commonly used memory elements in these circuits are time-delay
devices. There is no need to wait for a clock pulse.
 Therefore, in general, asynchronous circuits are faster than synchronous
sequential circuits.
 In an asynchronous circuit, events are allowed to occur without any
synchronization. And in such a case, the system may become unstable.
 The designs of asynchronous circuits are more tedious and difficult, their
use is rather limited.
 Sequential Circuits
 Memory elements used in clocked sequential circuits are flip-flops which
are capable of storing binary information.
 A flip-flop is capable of storing 1-bit of data. A sequential circuit may use
'n' flip-flops to store 'n' bits. It has two states, '1' or '0' state. It remains in that
state until an excitation is received to change the existing state.
 It has one or more inputs and two outputs (Q & Q'). The two outputs are
complementary to each other.
 If Q is '1' i.e., Q is Set, then Q' is 0 (reset). if Q is 0 i.e., Reset, then Q' is 1.
This means Q and Q' can never be same. If it happens by any chance, it
violates the definition of a flip-flop and such condition is called an undefined
condition. Normally, Q is called the state of the flip-flop and Q' is called
the complementary state.
 Flip-flops can be obtained by using NAND or NOR gates. The general block
diagram representation of a flip-flop is shown below.
 Bistable Multi-vibrator – Flip Flop
 A flip-flop is also known as a Bi-stable multi-
vibrator, which has two cross-coupled inverting
amplifiers, comprising of two transistors and four
resistors.
 If transistor T1 is initially turned ON (saturated) by
applying a positive signal through the Set input,
its collector will be at VCE (sat) (0.2 to 0.4 V).
Since, collector of T1 is connected to the base of
T2, which cannot turn T2 On. Hence, T2 remains
OFF (cut off) keeping its collector at VCC.
 If the initial signal at the Set input is removed, the
circuit will maintain T1 in the ON state and T2 in
the OFF state indefinitely, i.e., Q = 1 and Q' = 0.
 A positive signal applied to the Reset input at the
base of T2 turns it ON. T2 turns ON and T1 turns
OFF, resulting in a second stable state, i.e., Q = 0
and Q' = 1. In this condition the bi-stable multi-
vibrator is said to be in the Reset state.
 Latch
 Adjacent circuit uses two cross connected inverters G1
and G2. The output of G1 is connected to the input of G2
and the output of G2 is connected to the input of G1.
 Assuming that the output of G1 to be Q = 0, which is also
the input of G2 (A2 = 0). Therefore, the output of G2 will
be Q' = 1, which makes A1 = 1. Consequently Q = 0
which is consistent with initial assumption. Similarly, if Q
= 1, then Q' = 0.
 Conclusion: Q and Q' are always complementary.
 If the circuit is in '1' state, it continues to remain in this
state and vice versa is also true.
 Since this information is locked or latched in this circuit, it
is referred to as a Latch.
 This circuit has no way to enter the desired digital
information for storage.
 To make it possible, it has to be modified by replacing the
inverters with two input NAND gates/ two inputs of the
NAND gate have to be untied and one of them will be
used to SET or RESET the latch.
 SR Latch (NOR Gate Based)
Detailed Working
 An SR Latch is the basic building block of a Flip flop in the digital sequential
circuits. It is the simplest form of a storage register unit (memory).
 It is implemented using NOR or NAND gates in a cross coupled fashion.
SR Flip flop, implemented using NOR gates, has two inputs labeled
“S” for 'Set' “R” for 'Reset'
 An SR Flip flop has two useful states:
State-1: When S=1, R=0 → Set State Q=1 & Q'=0 is reached.
State-2: When S=0, R=1 → Reset State Q=0 & Q'=1 is reached.
State-3: An undefined state occurs, when both outputs are '1' (HIGH)
at the same time.
NOR Gate Truth Table

Not Used
 SR Latch (NOR Gate Based)
Detailed Working
 Case-1: S=1, R=0, Q=1, Q'=0 (Refer NOR Gate TT: When B=1; Q=0)

S=0, R=0, Q=1, Q'=0 (Last state of Q retained – Memory function)

 Case-2: S=0, R=1, Q=0, Q'=1 (Refer NOR Gate TT: When B=1; Q=0)

S=0, R=0, Q=0, Q'=1 (Last state of Q retained – Memory function)

 When asserted input, S or R is returned to 0, the flip flop retains its SET or
RESET state depending upon which input (S or R) was recently asserted to '1'.

Case-1

Case-2

Case-3 Not Used

NOR Gate Truth Table
 SR Latch (NOR Gate Based)
Detailed Working
 Case-3:
S=1, R=1: As per NOR GATE Truth Table, both Q & Q' will try to be =0,
but this violates the fact that both outputs are complement of each other.
Now bring S & R to resting state i.e. S= 0, R= 0:-
 Assuming Q =0, this will cause Q' to become '1'. Thus Q=0 & Q'=1
 Assuming Q=1, this will cause Q to become '1'. Thus Q=1 & Q'=0
Thus, when input condition S=1 & R=1 returns to resting state S=0 & R=0, it is difficult to
ascertain which stable state will be attained by the circuits as there are two possible
different output states. This uncertainty is not acceptable.
 Case 3 is not recommended for use and should be avoided by making sure
that both inputs are not '1' simultaneously.

Case-2

Case-1

Case-3 Not Used

NOR Gate Truth Table
 SR Latch (NOR Gate Based)
Detailed Working
 Truth Table of NOR gate based SR Latch is shown below.
 The last State for S= R=1 results in a forbidden state as both outputs try to be
'0', which violates the principle of outputs of the flip flop to be complimentary
in nature.
 In case S=R=1 condition is achieved and thereafter both inputs return to '0'
(S=0, R=0), the outputs of the flip flop will again be in indeterminate state as
explained in the previous slide.

Logic Symbol
of SR Flip Flop

(Memory State)
 S'R' Latch Using NAND Gate
 It has two cross-coupled NAND gates.

 When S’=0, R’=1, then Q = 1 & Q'=0 (SET state). When

S returns to '1', the SET state is retained i.e. Q=1

 When S’=1, R’=0, then Q = 0 & Q'=1 (RESET state).

When R returns to '1', RESET state is retained i.e. Q=0.

 When both inputs (Set & Reset) are 1, then it retains

the last state. Logic Symbol
of S'R' Flip Flop
 For change of state, Set or Reset input must go to 0.

'
Reset →

Set →

Undefined→ Not Used

'
 S'R' Latch Using NAND Gate
 Undefined Condition:
S=0 & R=0 is the undefined condition for NAND gate based SR Flip
flop and should be avoided.
With S=0 & R=0, both Q & Q' try to be '1' which is not acceptable.
 Difference between NAND & NOR Gate based Flip Flops:
Input signals for NAND based SR Flip flop are opposite to that of
NOR based flip flop i.e. inputs are complement of NOR latch inputs.
Hence, a NAND SR flip flop is also called S'R' Flip Flop.
Set & Reset inputs are flipped with respect Q & Q' outputs.

'

' Not Used

 Example of S'R' Output Waveform

 Example: Waveforms in adjacent figure are applied

to the inputs of a S'R' latch. Assuming initial state of Q
= 0, determine the Q waveform.
 Initially with SET = RESET =1, Q remains in the 0
state (initial state). LOW pulse occurring on the
RESET input at time T1 will have no effect because Q
is already in the cleared (0) state.
 Q goes to the HIGH state by a LOW pulse on the SET
input. This occurs at time T2 when SET goes LOW. At
T3, SET returns to HIGH, and Q remains in its new
HIGH state.
 At time T4, SET goes LOW again, there is no effect
on Q because Q is already set to the 1 state.
 Q will go to LOW by a LOW on the RESET input.
This occurs at time T5, When RESET returns to 1 at
time , Q remains in the LOW state.
 S'R' Latch Using NAND Gate
 Truth Table of NAND gate based S'R' Latch is shown below.
 The last State for S'= R'=0 results in a forbidden state as both outputs try to
be '1' which violates the principle of outputs of the flip flop to be
complimentary in nature.
 In case S'=R'=0 condition is achieved and thereafter both inputs return to
'1' (S'=1, R'=1), the outputs of the flip flop will again be in indeterminate state
as explained in the previous slide.

(Memory State)
 Comparison of SR & S'R' Flip Flops

 Comparing NOR flip flop (SR) and NAND Latch (S'R') - these two flip
flops operate in complement fashion of each other.
 To convert a NAND gate based Latch (S'R' Latch) to SR Latch
(behavior similar to NOR gate based), place an inverter at each input of
S'R' Latch (as shown).

Converting NAND gate based S'R' Latch

to behave like NOR gate Based SR Latch
 SR Flip Flop (with Control Input)
 Output state of a flip flop can change
inadvertently as soon as the inputs change.
 To obviate this problem, operation of the basic
flip-flop can be modified by adding an
additional input to control the behavior of the
SR flip flop, which determines when the output
state of the flip flop is changed.
 Generally, synchronous circuits change their
states only when clock pulses are present.
Clocked SR FF
 The circuit shown here consists of two AND
gates with a clock input to both AND gates.
When clock input is LOW, changes in S and R
inputs will not affect the state (Q) of the FF.
When clock input is HIGH, the changes in S
and R will affect the state of the FF.
 This way, any information,1 or 0, can be stored
in the flip-flop by applying a HIGH clock input
and be retained for any desired period of time NOR Gate Based SR FF
by keeping a LOW at the clock input. This type
of flip-flop is called a clocked S-R flip-flop.
 SR Flip Flop (with Control Input)
 Same S-R flip-flop can be constructed using
the basic NAND latch and two other NAND
gates.
 The S and R inputs control the states of the
flip-flop in the same way as described earlier
for the unclocked S-R flip-flop.
 The flip-flop only responds when the clock
signal occurs as it acts as an enable signal for
NAND Gate Based SR FF
the two inputs.
 As long as the clock input remains 0 the
outputs of NAND gates 1 and 2 stay at logic 1.
This 1 level at the inputs of NAND gates 3 & 4
retains the present state.
 The logic symbol of the S-R flip-flop is as
shown. It has three inputs: S, R, and CLK. The
CLK input is marked with a small triangle
denoting the fact that the circuit responds to an Logic Symbol of SR FF
edge or transition at CLK input.
 SR Flip Flop (with Control Input)
Logic symbol of the S-R flip-flop is shown below.
It has three inputs: S, R, and CLK.


CLK input is marked with a small triangle, which denotes that the circuit
responds to an edge or transition at CLK input.
Working of the S-R flip-flop can be expressed in the form of a truth table
assuming that CLK is enabling the inputs to the flip flop:-
Sn and Rn denote the inputs
Qn the output during the bit time 'n'
Qn+1 denotes next state after CLK pulse passes, i.e. at bit time 'n + 1'

No
Change
 SR Flip Flop (with Control Input)
(Detailed Working)
Following cases will be discussed in the subsequent slides to demonstrate
how the outputs of SR flip flop change with respect to its inputs:-
(a) When Control signal/CLK is not applied implying that it is LOW.
(b) When Control signal/CLK is applied – following four cases for
different values of S & R inputs are discussed in next few slides:-
(I) Case-1: When S =0, R=0
(II) Case-2: When S =0, R=1
(III) Case-3: When S =1, R=0
(IV) Case-4: When S =1, R=1

No
Change
 SR Flip Flop (with Control Input)
(Detailed Working)
Operation:
1
 When clock pulse is (0) not applied: the 0
No Change
flip-flop remains in its present state,
irrespective of inputs Sn & Rn, .
 When the clock pulse is (1) applied, 0
following 4 cases are discussed:-
Case 1.
When Sn = Rn = 0, the output remains 0 No Change
1
unchanged, i.e., Qn+1 = Qn.
Case 2.
When Sn = 0 and Rn = 1, the output of 0
1
NAND gate 1 becomes 1; Output of NAND 0
1
gate 2 will be 0. A '0' at the input of NAND 1
gate 4 forces the output to be 1, i.e., Q' = 1.
Q' goes to the input of NAND gate 3 to
make both the inputs of NAND gate 3 as '1',
which forces the output of NAND gate 3 to 0
be '0', i.e., Q = 0. 1 1
1 0
 SR Flip Flop (with Control Input)
(Detailed Working)
Case 3. 1
For Sn=1 and Rn=0 0
1
Output of NAND gate 2 → 1 and 1

Output of NAND gate 1 → 0,

1
This results in →
Output of NAND gate 3 → 1, i.e., Q = 1.
Q goes to the input of NAND gate 4 to make 1
1 0
both the inputs of NAND gate 4 as 1, which
0 1
forces its output to 0, i.e., Q' = 0.
Case 4.
For Sn=1 and Rn=1 1
0 1
Outputs of both NAND gate 2 → 0 1
Outputs of both NAND gate 1 → 0
A '0' at the input of both NAND gates 3 and 4 1
forces Q → 1 and Q' →1 .
When the CLK goes back to 0 (while S=R=1),
next state can not be determined, as it 1 1
0
depends on which gate (1 or 2) goes to '1' first. 1
1. Initially, S=R=0, the Q output is
assumed to be 0; that is Q0=0.
2. When the PGT (positive going
transition) of the first clock pulse
occurs (point a), S=R=0, so the FF is
not affected and remains in the state
Q=0 (i.e. Q=Q0).
3. At the second PGT of the clock pulse
(point c), the S=1, R=0 sets the FF to
the HIGH state.
4. Third PGT occurs at point 'e', when S =
0 and R = 1, this resets the FF to LOW
state.
5. Fourth PGT clock pulse (point g) sets
the FF once to the HIGH state.
6. At Fifth PGT clock pulse, S=1 & R = 0,
since, Q is already high, so it remains
in HIGH state.
7. S=R=1 condition should not be used
because it results in an ambiguous
condition.
SR Flip Flop – Working & Wave forms (same as last
slide)
 Difference Between Latch & Flip Flop
Latch
A Latch is asynchronous circuit whose output can change as soon as
the inputs are applied (or at least after a small propagation delay).
A Latch is level triggered.
Latches are useful for storing binary information and for designing
asynchronous sequential circuits. These are not used to realize
synchronous sequential circuits.

Flip-flop

A flip-flop changes state when a transition occurs in the control signal

(High to Low or Low to High (edge triggered).

Flip-flop can maintain a binary state indefinitely (as long as the power
is delivered to the circuit) or until directed by an input signal to change
the state
 Differences Between Flip Flops
 Major differences between various types of flip-flops are

Number of inputs they possess

Manner in which the input affect the output state

Types: S-R, D, J-K, and T. Basically D, J-K, and T are three

different modifications of the S-R flip-flop.
 Preset and Clear
When power to a flip-flop is turned ON, it is not known which state (Set or
Reset) will be assumed by the circuit, hence it's beginning state is
uncertain.
But in most applications, it is required to initially have the flip flop in a
defined “Set” or “Reset” state.
Assigning initial state to a flip flop is done by using the direct or
asynchronous inputs, referred to as Preset (Pr) and Clear (Cr) inputs.
These inputs may be applied at any time between clock pulses and are not
required to be in synchronized with the clock.
Logic symbol of an S-R flip-flop with Pr and Cr inputs is shown below.
Bubbles for Pr and Cr inputs indicate active low inputs.
 Preset and Clear
 If Pr = 0 and Cr = 1, the output of NAND gate 3 is forced to be 1, i.e.,Q = 1
and the flip-flop is Set, overwriting the previous state of the flip-flop.
 If Pr = 1 and Cr = 0, the output of NAND gate 4 is forced to be 1, i.e., Q' =1
and the flip-flop is Reset, overwriting the previous state of the flip-flop.
 Once the initial state has been assigned to the flip-flop, Preset and Clear
inputs must be restored back to logic 1 for normal operation.
 If Pr = Cr = 1, the circuit operates according to the table shown below.
 Condition Pr = Cr = 0 must not be applied as it leads to uncertain state.
 D Flip Flop
 D flip-flop has only one input referred to as the
D input, or data input, and two outputs Q and
S
Q'.

 It transfers the data at the input after a delay of

one clock pulse at the output Q. Hence, it is
referred to as a delay input and the flip-flop
gets the name Delay (D) flip-flop.
R
 It is constructed from an S-R flip-flop by simply
incorporating an inverter between S and R such
that the input of the inverter is at the S end and
the output of the inverter is at the R end.

 This ensures that undefined condition S=R=1 of

the S-R flip-flop does not occur in the D flip-
flop.

 D flip-flop is either used as a delay device or as

a latch to store one bit of binary information.
 D Flip Flop
Working of D Flip Flop
1 1
Case 1. If the CLK input is low, the value of the 1
D input has no effect, since the S and R inputs 0
of the basic NAND flip-flop are kept as 1.
1
Case 2. If the CLK = 1, and D = 1,
0
NAND gate 1 produces 0, which forces the 1
output of NAND gate 3 as 1. 1 0
Both inputs of NAND gate 2 are '1', which
gives the output of gate 2 as 0. Hence, the
output of NAND gate 4 is forced to be 1, i.e.,
Q = 1,
Both the inputs of NAND gate 5 are 1 and
the output is 0, i.e., Q' = 0.
Thus, when D = 1, after one clock pulse
passes Q = 1, which means the output follows
D.
 D Flip Flop
0 0
Case 3. If the CLK = 1, and D = 0, 0
1
NAND gate 1 produces 1. Both the inputs of 1 1
NAND gate 3 are 1, which make output of
NAND gate 3 as '0'. Now one input of NAND
gate 5 is at '0' and irrespective of the state of
another input, NAND gate 5 output goes to '1' 1 1
0
i.e. Q' =1 0
1
Since D = 0, output of NAND gate 2 becomes
'1', which is the first input to NAND gate 4.
Second input of NAND gate 4 comes from Q' -
1. Thus, both inputs of gate 4 are 1 and its
output becomes 0, i.e., Q = 0
Hence, when D = 0, after one clock pulse
passes Q = 0, which means the output again
follows D.
 D Flip Flop
 A simple way to construct a D flip-
flop using an S-R flip-flop is as
shown.

 The logic symbol of a D flip-flop is

shown in the figure. Triangle is a
symbol that denotes the fact that
the circuit responds to an edge or
transition at CLK input.
 A D flip-flop is most often used in
the construction of sequential
circuits like registers.
 D Flip Flop Operation
 Operation of a Positive Edge Triggered D
flip-flop: Q will go to the same state that is
present on the D input when a PGT occurs at
CLK.
 Assuming Q is initially HIGH. When the first
PGT occurs at point a, the D input is LOW;
thus, Q will go to the 0 state.
 Even though the D input level changes
between points a and b, it has no effect on Q.
 At b, PGT occurs again, Q goes HIGH
because D is HIGH at that time. Q stores this
HIGH until the PGT at point c causes Q to go
LOW because D is LOW at that time.
 In a similar manner, the Q output takes on the
levels present at D whenever PGTs occur at
points d, e, f, and g.
 For negative edge triggered flip flop, all
changes will occur on active negative clock
edge.
 D Flip Flop
Example: Determine the Q waveform for a D latch
with the EN and D inputs as shown. Assume that Q =
0 initially.
Prior to time T1, EN is LOW and Q = 0 and cannot
change even though D is changing.
During the interval T1 to T2, EN is HIGH, Q will
follow D. Thus, Q goes HIGH at T1 and stays
there because D is not changing.
At T2, EN returns to LOW, so Q will remain HIGH
as long as EN is LOW.
At T3, EN goes HIGH, Q will follow the changes
in the D input until T4 when EN returns LOW.
During the interval T3 to T4, the Q output follows
variations in D input.
At T4, EN becomes LOW, Q remain at the 0 LOW
and will not respond to changes in D until EN
remains LOW.
 JK Flip Flop
 A J-K flip-flop is a refinement of S-R flip-flop.
 It makes use of undefined state of S-R flip-flop, i.e., Sn = Rn = 1 in to a
defined state by providing an additional layer of cross connected feedback
loop from output to input.

SR FF converted to JK FF
 JK Flip Flop
 In JK flip flop, inputs J and K are ANDed with Q' and Q respectively to
obtain the inputs for S and R respectively. Logic Symbol of JK flip flop is
shown below.
 Inputs J and K behave like inputs S and R to set and reset the flip-flop
respectively.
 JK flip flop makes use of all possible combinations of inputs unlike SR flip
flop in which one state cannot be used. This state is when J = K = 1, the
flip-flop operates in toggle mode.

S’

R’
 JK Flip Flop
 JK flip-flop implementation with AND gate
input on basic (NOR gate based) SR flip flop
is given below. Qn & Qn' outputs of the flip
flop are fed back (cross connected) as inputs
at two levels. Hence these are also treated
as inputs for generating the detailed truth
table given below.
 The truth table of JK FF using basic SR FF
with ANDed inputs is given below:- Truth Table of NOR gate based SR FF

Memory S=JQ'
J
Memory

K R=KQ

Toggles
Toggles
 JK Flip Flop
 JK flip-flop can be implemented by providing additional input to NAND
gates based SR flip flop.
 Qn & Qn' outputs of the flip flop are fed back (cross connected) as inputs at
two levels.

S’

R’
 JK Flip Flop
 Truth table for JK flip flop is given below:-

S’

No Change

Reset

Set
R’
Toggle State
 JK Flip Flop Operation
 At 'a', CLK hoes HIGH and J=0, K=1, Q resets and becomes LOW.
 At 'c', CLK goes HIGH and J=1 K=1, so Q toggles to HIGH.

 At 'e', CLK goes HIGH again, now J=1 & K=0, Q remains HIGH.

 At 'i', CLK goes HIGH again and now J=K=1, Q toggles to LOW.

 At 'k', CLK hoes HIGH and J=K=1, this makes Q to toggle to HIGH.

I
n
p
u
t
s

O
u
t
p
u
t
 JK Flip Flop Operation
Example: Determine the Q output for a
negative-edge-triggered J-K flip-flop for
the input wave forms shown in the Figure.
Assume that tH = 0 and that Q = 0 initially.
FF responds only at T2, T4 , T6 and T8.


At T2 , Q will respond to J = K = 0 the

condition present just prior to T2.
At T4, Q will respond to J=1, K=0 the
condition present just prior to T4.
At T6, Q will respond to the J=0 K =1
condition present just prior to T6.
At T8, Q responds to J = K = 1.

 JK Flip Flop Timing Example
 J-K FF has a negative edge triggered
(NGT) clock input. It has active-LOW
asynchronous inputs (Preset & Clear). J
and K inputs are HIGH.
 Determine the Q output in response to the
input wave forms. Assume Q is initially
HIGH..
 PRE' & CLR' inputs are inactive when
HIGH.
 a - Synchronous toggle on NGT of CLK
 b - Asynchronous set on PRE = 0
 c - Synchronous toggle
 d - Synchronous toggle
 e - Asynchronous clear on CLR = 0
 f - CLR overrides the NGT of CLK
 g - Synchronous toggle
 Race Around Condition of JK Flip Flop
 Inherent problem of S-R flip-flop (for S = R = 1) is eliminated by using the feedback
connections from the outputs to the inputs (JK FF).
 Excitation table of JK Flip Flop had an assumption that the inputs will not change
during the time when clock pulse (CLK = 1). This consideration is not true because of
the feedback connections.
 Race around condition occurs in JK flip-flop when both inputs J=K=1 (Toggle
Condition) and CLK=1. After time ∆t = propagation delay of two NAND gates, the
output Q toggles to '0'. After another time ∆t, the output Q toggles again to '1'.
 Hence, during the time duration of TP of the clock pulse, the output Q oscillates
between 0 and 1 many times.
 Thus, at the end of the clock pulse, state of the output Q is not certain. This situation
is referred to as a Race-around condition.
 Race Around Condition of JK Flip Flop
 Generally, the propagation delay of TTL gates is of the order of nanoseconds.
 So if the clock pulse is of the order of microseconds, then the output will
change many times within the duration of the clock pulse.
 So the Race-around condition can be avoided if Tp < ∆t < T.
 Since ICs have small propagation delay as compared to the duration of the
clock pulse, it may be difficult to satisfy the above condition.
 A more practical way to avoid the problem is to use:
Have edge triggered (+ve or -ve) flip flops or
Master-slave (M-S) configuration (effect is same as that of a negative
edge triggered flip flop).
 Master-Slave JK Flip Flop
 A Master-Slave (M-S) flip-flop is a system of two flip-flops—one being
designated as master and the other is the slave.
 Clock pulse is applied to the Master and the inverted form of the same Clock

pulse is applied to the slave.

 Master-Slave JK Flip Flop
 When CLK = 1, the first flip-flop (i.e., the master) is enabled and the outputs
Qm and Q'm respond to the inputs J and K according to JK FF table.
At this time the second flip-flop (i.e., the slave) is disabled because the CLK is LOW
to the second flip- flop.

 When CLK = 0, the master FF becomes disabled and the slave becomes
active. The outputs Q and Q' of slave FF follow the outputs Qm and Q'm
respectively.
 The second flip-flop is referred as Slave Flip Flop as it just follows the first

one which is referred as Master Flip Flop.

 Master-Slave JK Flip Flop
 In Master-Slave (M-S) flip-flop, inputs to NAND gates 5 and 6 do not change at the
time of application of the clock pulse. This prevents race-around condition.
 State of the master-slave flip-flop, changes at the negative transition (trailing edge)
of the clock pulse. Hence, it becomes negative triggering master-slave flip flop. The
logic symbol of a negative edge master-slave is shown below on right.
 Negative edge triggered MS-FF can be changed to a positive edge triggering MS-FF
by adding additional inverter to the system. Thus the two inverters will be at —one
before the clock pulse is applied to the master and another one in between the
master and the slave.
 System of master-slave flip-flops is not restricted to J-K master-slave only. There
may be an S-R master-slave or a D master-slave, etc., in all of them the slave is an
SR flip-flop, whereas the master changes to J-K or S-R or D flip-flops.

Logic Symbol of a -ve edge

Triggered Master-Slave JK FF
 T Flip Flop
 If the two inputs J and K of a J-K flip-flop are tied together, it is called a T-flip-flop.
Thus, it is very easy to convert a JK flip flop to a functionally equivalent T flip
flop by just connecting J & K inputs together. Thus,
when T = 1, it is like J=1 & K=1 and the flip flop toggles.
When T=0, it is like J=0 & K=0, leading to no change in its state
 Hence, a T flip-flop has only one input T and two outputs Q and Q'. The flip-flop
has the ability to toggle between two states —
When T is high, FF toggles with each clock pulse and
When T is Low, FF remains in whatever state it was before (memory
state).
 Since T FF has two states, it is a very good option to use in design of counters
and in sequential circuits design where switching operation is required.

J
T

K
 T Flip Flop

T- Flip Flop with Preset and Clr inputs

Block Diagram of the T-Flip Flop Logic Symbol of T -Flip Flop

 Toggling Mode of SR & D Flip Flops
Toggle Mode for SR FF:
The condition S = R = 1 is not allowed, hence an S-
R flip-flop cannot work as T-flip-flop. If Q and Q'
outputs are connected to R & S inputs of S-R flip-
flop, it can be made to work in toggle mode.
When Q = 1 and Q' = 0, then S = 0 and R = 1, with
the clock pulse the S-R FF resets to Q=0 and Q'=1.
When Q=0 and Q' = 1, then S = 1 and R = 0, with the
clock pulse the S-R FF sets to Q=1 and Q'=0. Thus,
SR FF toggles between 1 & 0 with each clock pulse.
Toggle Mode for D FF
Q' output of a D FF is connected to D input for
operating D FF in toggle mode.
When Q = 1 and Q' = 0, then D = 0, with the clock
pulse the D flip-flop gets reset to Q = 0 and Q' = 1.
When Q = 0 and Q' = 1, then D = 1, with the clock
pulse the D flip-flop resets to Q = 1 and Q' = 0.
Hence, the FF toggles with each clock pulse.
 Triggering of Flip Flops
 Flip-flops are synchronous sequential circuits which work with the
application of a synchronization mechanism, called Clock.
 Based on the specific interval or point in the clock during or at which
triggering of the flip-flop takes place, there are two classifications -
Level Triggering and
Edge Triggering.
 Triggering of Flip Flops
Level Triggering of Flip-flops
If a flip-flop is enabled when a clock pulse goes HIGH and remains enabled

for the duration when Clock=HIGH, the FF is said to be a Level Triggered

flip-flop. It has two variants:-
If the flip-flop changes its state when the clock pulse is positive, it is termed
as a positive level triggered flip-flop.
If a NOT gate is introduced in the clock input, then the FF changes its state
when the clock pulse is negative and is termed as a negative level triggered
FF.
Drawback of Level Triggering:
As long as the clock pulse is active, the flip-flop changes its state as many

times as the change in inputs.

If the inputs do not change when the clock is active, the output remains stable.

If the inputs change at a frequency higher than the clock frequency, the output of

the flip-flop will change multiple times during the time clock is active.
This draw back can be overcome by using either master-slave configuration or

edge-triggered flip-flop.
 Edge Detector
 Edge Detector, shown below, produces a narrow positive going spike (CLK*) coincident
with the active transition of the CLK input pulse. Pulse-steering circuit “steers” the spike
through to the SET or the RESET input of the latch in accordance with the levels present at S
and R.
 Generation of CLK* signal for triggering of FF on positive edge of clock CLK:
– The INVERTER produces a delay of a few nanoseconds so that the transitions of CLK
occur a little bit after those of CLK.
– The AND gate produces an output spike that is HIGH only for the few nanoseconds
when CLK and CLK are both HIGH.
– The result is a narrow pulse at CLK*, which occurs on the positive edge of CLK.

CLK*
 Edge Detector
 Generation of CLK* signal for triggering of FF on negative edge of clock CLK:
The INVERTER produces a delay of a few nanoseconds so that the transitions of
CLK occur a little bit after those of CLK.
 The INVERT-AND (NOR) gate produces an output spike that is HIGH only for the
few nanoseconds when CLK and CLK are both HIGH.
 The result is a narrow pulse at CLK*, which occurs on the negative edge of CLK.

CLK*
PGT –Positive Going Trigger NGT –Negative Going Trigger
 Characteristic Equations of SR Flip Flop
Characteristic Equation of the S-R flip-flop is obtained from the
characteristic table with the help of the Karnaugh map for Qn+1:-

Qn+1 = S + R'Qn

Note: Fill the K-Map using adjacent truth table

 Characteristic Table & Equation of a D
Flip Flop
 The characteristic table of a D flip-flop is given below. It presents the
next state of the flip flop wit respect to present input and present output
state Qn.
 The Characteristic equation of the D flip-flop is obtained from the

characteristic table with the help of the Karnaugh map:-

Qn+1 = D
 Characteristic Table & Characteristic
Equation of JK Flip Flop
 The characteristic table of a J-K flip-
flop is prepared for three inputs (J, K
and present state Qn of the flip flop).
 From the characteristic table,
characteristic equation of the J-K
flip-flop is found by Karnaugh map
method.
 From the Karnaugh map, the
characteristic equation of the J-K
flip-flop is
Qn+1 = JQ'n + K'Qn
 Characteristic Table & Equation of T-FF

 The characteristic table of a T flip-flop is given below.

 From the characteristic table, characteristic equation for next state
Qn+1 of the T flip-flop is derived using Karnaugh map:
Qn+1 = TQ'n + T'Qn
 Truth Table, Characteristic Table and
Excitation Table of SR Flip Flop

Truth Table Characteristic Table Excitation Table

 Truth Table, Characteristic Table and
Excitation Table of JK Flip Flop

Truth Table Characteristic Table Excitation Table

 Excitation Table of a Flip Flop
 Truth Table of a FF is also referred to as the Characteristic table of the FF. While
designing sequential circuits with known present state and next state of a FF, input
conditions to achieve the desired output (next) state need to be worked out.
 For example, if the output of an S-R flip-flop before applying the clock pulse is Qn=1
and it is desired that output should not change after the clock pulse is applied. To
achieve this, input conditions obtained from the characteristic table of S-R FF are:
I/p Condition-1: S = R = 0 I/p Condition-2: S = 1, R = 0
From above, it can be concluded that the R must be 0, while S may be 0 or 1 (don’t-
care) to achieve the specified output state.
 Similarly, for all possible situations, the input conditions can be found out. A
tabulation of these conditions is known as an Excitation Table.
End