1

2.0
Features of CMOS
2.1 PMOS & NMOS
2.2 Well
2.3 Isolation
 2

Figure 2.0 : CMOS cross section showing NMOS (left) and PMOS (right) transistor
(Retrieved from: https://www.researchgate.net/figure/CMOS-cross-section)
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2.1 PMOS & NMOS

PMOS
o Made up of p-type source and drain and a n-type substrate.
o Arranged in Pull Up Network (PUN) - Pull up Network is used to make output as
logic High.
o A high voltage on the gate will cause a PMOS not to conduct, while a low
voltage on the gate will cause it to conduct.
o As the mobility of PMOS transistor is lower than NMOS transistor, W/L ratio of
PUN transistors is higher.
o Logic gates and other digital devices implemented using PMOS are said have
PMOS logic.
o PMOS technology is low cost and has a good noise immunity.
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2.1 PMOS & NMOS

NMOS
o Made up of n-type source and drain and a p-type substrate.
o Arranged in Pull Down Network (PDN) - Pull down network is used to make output as
logic Low.
o When a high voltage is applied to the gate, NMOS will conduct, when a low voltage is
applied in the gate, NMOS will not conduct.
o As the mobility of NMOS transistor is higher than PMOS transistors, W/L ratio of PDN
transistors is lower.
o NMOS logic gates dissipate static power when the circuit is idling, since DC current
flows through the logic gate when the output is low.
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2.2 Well
Purposes of well in CMOS
o To make fabrication of both N and P channel transistor on the same substrate.
o To prevent the parasitic pn junction from turn on.
o To adjust or tune the important device parameters to the device requirements.
o As a resistor in some technology applications.
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2.2 Well
Different types of CMOS well

Retrograde
P-Well N-Well Twin Well
Well
Technology Technology Technology
Technology
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2.2 Well
2.2.1: P-Well Technology
o Involves the creation of p-region in n-type substrate for the fabrication of n-channel
transistor.
o P-wells are formed by introducing a p-type dopant into an n-substrate.
o P-well doping concentration normally done at 5 to 10 times higher than n-substrate doping
level.
 8

Figure 2.2.1: After front-end process P-well CMOS technology

(Retrieved from: https://www.elprocus.com/the-fabrication-process-of-cmos-transistor/)
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2.2 Well
2.2.2: N-well Technology
o Involves the creation of n-regions in p-type substrate for the fabrication of p-channel
transistor.
o The n-wells are formed by implanting a n-type dopant into an n-substrate.
 10

Figure 2.2.2: N-Well CMOS technology

(Retrieved from: https://www.elprocus.com/the-fabrication-process-of-cmos-transistor/)
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2.2 Well
2.2.3: Twin Well Technology
o Two separate wells are formed for n and p-channel transistors on a lightly
doped substrate.
o The substrate maybe either a lightly doped n or p-type material, or a thin, lightly
doped epitaxial layer.
o Each of the wells dopants is implanted separately and then driven to the desired
depth.
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Figure 2.2.3.1: After front-end process, twin-well CMOS technology

(Retrieved from: https://www.electronics-tutorial.net/CMOS-Processing-Technology/Twin-tub-Process/)
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Figure 2.2.3.2: After front-end process, Twin-Well CMOS on Epi substrate technology
(Retrieved from: https://www.edgefx.in/understanding-cmos-fabrication-technology/)
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2.2 Well
2.2.3.1: Advantages of Twin Well Fabrication
o Sub-micron CMOS technology.
o Doping profile for each device can be set independently.
o Compatibility with advanced isolation structure (trench and SEG), allow closer n+ to p+
spacing design rules i.e denser circuit.
o Substrate can be changed without changing the process flow.
o Enable the implementation of self aligned channel stop.
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2.2 Well
2.2.4: Retrograde Well Technology
o Use high energy implant, followed by short annealing step. Well formed by this technique
is called Retrograde Well.
o Temperature cycle of subsequent process is tightly controlled.
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Figure 2.2.4: After front-end process, Retrograde Well CMOS technology

(Retrieved from: http://www-inst.eecs.berkeley.edu/~ee143/sp06/lectures/Lec_21.pdf)
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2.2 Well
2.2.4.1: Advantages of Retrograde Well
o High packing density (smaller n+ to p+ rules).
o Lower leakage current (punch through susceptibility improved).
o Lateral diffusion of Boron is eliminated, reduce Boron encroachment into active.
o Higher field device threshold voltage due to less Boron segregation into oxide.
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2.3 Isolation
» Thermal grown oxide is mainly used as isolation material in semiconductor
fabrication.
» For the isolation of neighboring MOS transistors there exist two techniques,
namely Local Oxidation of Silicon and Shallow Trench Isolation.
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2.3 Isolation
2.3.1: LOCOS
o Local Oxidation of Silicon (LOCOS) is the traditional isolation technique.
o The main drawback of this technique is the so-called bird's beak effect and the
surface area which is lost to this encroachment.
o The advantages of LOCOS fabrication are the simple process flow and the high oxide
quality because the whole LOCOS structure is thermally grown.
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Figure 2.3.1: Process sequence for LOCOS

(Retrieved from: http://www.iue.tuwien.ac.at/phd/hollauer/node7.html)
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2.3 Isolation
2.3.2: Shallow Trench Isolation (STI)
o STI is preferred isolation technique because it completely avoids the bird’s beak
shape characteristic.
o STI is more suitable for increased density requirements because it allows to form
smaller isolation regions.
o The price for saving space with STI is the large number of different process
steps.
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Figure 2.3.2: Steps in STI process flow

(Retrieved from: : http://www.iue.tuwien.ac.at/phd/hollauer/node7.html)