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Low-power FinFET Circuit

Design
Niraj K. Jha
Dept. of Electrical Engineering
Princeton University

Joint work with: Anish Muttreja and


Prateek Mishra
Talk Outline
• Background
• Motivation: Power Consumption
• FinFETs for Low Power Design
• Vth Control through Multiple Vdd’s
(TCMS)
• Extension of TCMS to Logic Circuits
• Conclusions
2
Why Double-gate Transistors ?
Feature size 32 nm 10 nm
Bulk CMOS DG-FETs
Gap Non-Si nano devices

• DG-FETs can be used to fill this gap


• DG-FETs are extensions of CMOS
– Manufacturing processes similar to CMOS
• Key limitations of CMOS scaling addressed through
– Better control of channel from transistor gates
– Reduced short-channel effects
– Better Ion/Ioff
– Improved sub-threshold slope
– No discrete dopant fluctuations

3
Different Types of DG-FETs

Source: ( Hollis, Boston University) 4


What are FinFETs?
• Fin-type DG-FET
– A FinFET is like a FET, but the channel has been “turned on its edge”
and made to stand up

Si Fin

5
FinFET 3-D Structure

Earliest FinFET processes: both


gates inherently connected

Source: (Ananthan, 2004) 6


Independent-gate FinFETs
Oxide insulation
Back Gate

• Both the gates of a FET can be independently controlled


• Independent control
– Requires an extra process step
– Leads to a number of interesting analog and digital circuit
structures

7
FinFET Width Quantization

• Electrical width of a FinFET


with n fins: W = 2*n*h
• Channel width in a FinFET is
quantized
• Width quantization is a
design challenge if fine
control of transistor drive
strength is needed
–E.g., in ensuring FinFET structure
stability of memory Ananthan, ISQED’05
cells
8
Talk Outline
• Background
• Motivation: Power Consumption
• FinFETs for Low Power Design
• Vth Control through Multiple Vdd’s
(TCMS)
• Extension of TCMS to Logic Circuits
• Conclusions
9
Motivation: Power Consumption
• Traditional view of CMOS power
consumption
– Active mode: Dynamic power (switching +
short circuit + glitching)
– Standby mode: Leakage power
• Problem: rising active leakage
– 40% of total active mode power consumption
(70nm bulk CMOS) †
†J. Kao, S. Narendra and A. Chandrakasan, “Subthreshold leakage modeling and reduction
techniques,” in Proc. ICCAD, 2002.

10
Low-power Design Techniques
• Standby mode
– Examples: Sleep transistor insertion, clock gating,
minimum leakage vector application
– Interfere with (disable/slow) circuit operation
– Do not address active mode leakage
• Active mode: Circuit optimization
– Examples: Gate sizing, Multiple Vdd/Vth
– Respect circuit operations and timing constraints
– Can be used to reduce active mode leakage

What opportunities do FinFETs provide us ?

11
Talk Outline
• Background
• Motivation: Power Consumption
• FinFETs for Low Power Design
• Vth Control through Multiple Vdd’s
(TCMS)
• Extension of TCMS to Logic Circuits
• Conclusions
12
FinFETs for Low-power Design
• FinFET device characteristics can be
leveraged for low-power design
– Static threshold voltage control through back-
gate bias
– Area-efficient design through merging of
parallel transistors
• Independent control of FinFET gates also
provides novel circuit design opportunities

13
Logic Styles: NAND Gates

SG-mode NAND IG-mode NAND

IG-mode
pull up
pull up bias
voltage

LP-mode NAND IG/LP-mode NAND


pull down LP-mode
bias voltage pull down 14
Comparing Logic Styles
Design Mode Advantages Disadvantages
SG Fastest under all load High leakage† (1μA)
conditions
LP Very low leakage Slowest, especially under
(85nA), low switched load. Area overhead
capacitance (routing)
IG Low area and switched Unmatched pull-up and
capacitance pull-down delays.
High leakage (772nA)
IG/LP Low leakage (337nA), Almost as slow as LP mode
area and switched
capacitance

Average leakage current for two-input NAND gate (Vdd = 1.0V)

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FinFET Characteristics

Simulated Id Vs. Vgs


characteristics for
FinFETs at varying
back-gate reverse
biases

• LP-mode leakage is 10 times lower than SG-mode


• LP-mode delay (∞ 1/Ion) is twice that of SG-mode
• IG-mode Ion is not much better than LP-mode
Ioff is a strong function of back-gate reverse bias but Ion is not 16
Back-gate Bias Voltage
• Value of back-gate bias
voltage affects speed
and leakage
• Heuristic: compare LP-
mode inverter delay and
leakage
• Bias values
– Pull-down= -0.2 V
– Pull-up = Vdd + .18V
Delay and leakage power variation (1.18V). Adjusted to
with back-gate bias voltage for
LP-mode FinFET inverter match delays
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Technical Challenges in FinFET-
based Circuit Design
• Wide variety of logic styles possible (can be
used simultaneously)
– No comprehensive circuit-level comparisons available
• Circuit synthesis challenges
– Industry-standard standard cell-based synthesis is
often suboptimal
– FinFET width quantization is based on solving a
convex integer formulation†
• Complex
• Does not handle all logic styles

†B. Swahn and S. Hassoun, ``Gate sizing: FinFETs vs 32nm bulk MOSFETs,” in Proc. DAC, 2006

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Our Approach
• Construct FinFET-based
32 nm PTM
32nm PTM Logic
Logicgate
gate Synopsys technology libraries
inFET models
FinFET
FinFETmodels
models designs
designs • Extend linear programming
based cell selection† for FinFETs
Delay/power • Use optimized netlists to
characterization in compare logic styles at a range
Benchmark
SPICE of delay constraints

Minimum-delay SG-mode
IG SG synthesis in netlist
Synopsys libraries Design Compiler
Power-optimized
IG/LP LP
mixed-mode netlists

Linear programming SG+ SG+LP


†D. Chinnery and K. Keutzer, based cell selection IG/LP SG+IG
“Linear programming for sizing, Vdd
and Vt assignment,” in Proc.
ISLPED, 2005. 19
Power Consumption of Optimized Circuits

Estimated total power


consumption for
ISCAS’85 benchmarks
Vdd = 1.0V, α = 0.1, 32nm
FinFETs

Available modes

Total power savings Leakage power savings


• 110% arrival time (a.t.) (34%) • 120% a.t. (68.5%)
• 200% a.t. ( 47.5%) • 200% a.t. (80.3%)
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Optimized Circuit Constitution

Fraction of cells in different


FinFET modes in power-
optimized FinFET circuits

Available modes

• SG-mode cells are largely replaced by cells in other modes


– SG-mode cells only needed on critical paths
• Utilization of IG/LP-mode cells is higher than IG cells
– Result of unmatched delay and higher leakage of IG-mode cells 21
compared to IG/LP-mode cells
Area Requirements for Optimized
Circuits
+18.8% +18.0%

22
Talk Outline
• Background
• Motivation: Power Consumption
• FinFETs for Low Power Design
• Vth Control through Multiple Vdd’s
(TCMS)
• Extension of TCMS to Logic Circuits
• Conclusions
23
Future of Interconnect Power

• Interconnect power dissipation is projected


to dominate both dynamic and static power
– Assorted projections from literature-
• Interconnect switched capacitance may be 65-80%
of total on-chip switched capacitance at the 32nm
node [1]
• In power-optimized buffered interconnects at 50nm,
leakage power consumption may be > 80% of total
interconnect power [2]
[1] N. Magen et al., Interconnect Power Dissipation in a Microprocessor,
System-level Interconnect Prediction, 2004
[2] K. Banerjee and A. Mehrotra, Power Dissipation Issues in Interconnect
Performance Optimization for Sub-180 nm Designs, Symp. VLSI Circuits, 24
2002
Gate Coupling

• Linear relationship between threshold voltage and back-


gate voltage in the subthreshold region
– Stronger than the square root relationship between
body bias and threshold effect Vth Vb observed in
bulk-CMOS
25
Dual-Vdd FinFET Circuits

• Conventional low- Reverse bias


Vgs=+0.08V
Higher Vth

power principle:
1.08V 1V
– 1.0V Vdd for critical logic, Leakage
0.7V for off-critical paths current
Vin
• Our proposal:
overdriven gates
– Overdriven FinFET gates
leak a lot less! Overdriven
inverter

26
TCMS
• Using only two Vdd’s saves leakage only in
P-type FinFETs, but not in N-type FinFETs
• Solution
– Use a negative ground voltage (VHss) to
symmetrically save leakage in N-type FinFETs
– Vdd > Vdd
H L Vdd
H VddL

– VssH < VssL


Symmetric
threshold control
VddH 1.08V
for P and N
VddL 1.0V
VssH -0.08V
L
VssH VssL
Vss 0.0V
TCMS buffer
Voltage Level Conversion
• Static leakage in multiple-Vdd designs
– Low-Vdd inputs must be up-converted to high-
Vdd before being used to drive high-Vdd
inverters to avoid static leakage
– Dedicated level converters inserted between
buffers must be sized prohibitively large in
order to avoid delay penalties [1].
• Level conversion is built into high-Vdd
inverters through the use of high-Vt
FinFETs
[1]. K. H. Tam and L. He, Power-optimal Dual-Vdd Buffered Tree Considering 28
Buffer Stations and Blockages, DAC 2005
Exploratory Buffer Design
• Size of high-Vdd inverters kept small to minimize
leakage in them
• Wire capacitances not driven by high-Vdd inverters
• Output inverter in each buffer overdriven and its size
(and switched capacitance) can be reduced
• High- and low-Vdd inverters alternate, providing
maximum opportunities for power savings

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Link Design
• SPICE simulation to minimize power
consumption in TCMS link while remaining
within 1% of the delay of the single Vdd link
Single
Parameter TCMS Change
Vdd
0.199m
Link length(lopt) 0.199mm 0
m
Inverter widths
42, 84 30, 50 -36.5%
(s1, s2)
Delay (ps) 12.19 12.27 0.65%
Power (μW) 1080 647 -40% 30
Interconnect Synthesis
• Problem: Insert buffers on a given wiring
tree to meet a given delay bound while
minimizing total power consumption
• Two types of buffers considered
– TCMS buffers
– Dual-Vdd buffering scheme†
• A van Ginneken-style dynamic
programming buffer insertion algorithm
developed
†Y. Hu et al, Fast Dual-Vdd Buffering based on Interconnect Prediction 31
and Sampling, SLIP 2007
Power Savings

Power Savings
component
Dynamic -29.8%
power
Leakage 57.9%
power
Total power 50.4%

• Benchmarks are nets extracted from real layouts


and scaled to 32nm
http://dropzone.tamu.edu/~zhouli/GSRC/fast_buffer_inse
rtion.html 32
Fin-count Savings
700000

600000
Number of fins

500000

400000

300000 Dual Vdd


200000 TCMS

100000

0
p1 r1 p2 r2 r3 r4 r5 Average

• Transistor area is measured as the total


number of fins required by all buffers
• TCMS can save 9% in transistor area
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Talk Outline
• Background
• Motivation: Power Consumption
• FinFETs for Low Power Design
• Vth Control through Multiple Vdd’s
(TCMS)
• Extension of TCMS to Logic Circuits
• Conclusions
34
Traditional Dual-Vdd Dual-Vth
Schemes
• Logic gates on the critical path driven with
high-Vdd and low-Vth; those on the non-
critical path with low-Vdd and high-Vth
• Exponential increase in leakage current
• Overhead of level converter delay and
power

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TCMS Extension
H
Vdd • VddH=1.08V
VLdd • VssH= -0.08V
V1
H
Vss V1' • VddL =1.0V
H
Vdd • VssL=Gnd
V2'
V2 L
Vss
H
Vss

• Overdriven gates are faster
I D  (VGS  Vt )
• Overdriven gates leak less I L  exp(VGS  Vt ) 36
Logic Library Design
L H
Vdd Vdd

a a

b b

L
Vss VHss

• FinFETs connected to input-a • FinFETs connected to input-a cannot


follow TCMS exploit TCMS
• FinFETs connected to input-b • FinFETs connected to input-b have high
cannot exploit TCMS static leakage
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Logic Library Design (Contd.)
L H
Vdd Vdd

a a

b b

L
Vss VHss

• Level conversion may be used to restore signal to VddH


• Level converters not an attractive option in TCMS
• Level conversion can be built into logic gates through the use of
high-Vth FinFET
38
Logic Library Design (Contd.)
L H
Vdd Vdd

a a

b b

L
Vss VHss
• Two-input NAND gate of a given size has five design variables:
– Supply voltage
– Gate input voltage for input-a
– Gate input voltage for input-b
– Vth for FinFETs connected to input-a
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– Vth for FinFETs connected to input-b
Logic Library Design (Contd.)
L
Vdd

L
Vss

• 32 NAND gate modes possible


• Certain combinations not allowed (High-Vdd gate with low-Vth transistors
cannot have high input voltage swings)
• 25 NAND and NOR gate modes
• 7 INV gate modes
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• For each NAND, NOR and inverter mode: X1, X2, X4, X8 and X16 sizes
Optimization Flow
Combinational gate
Shorted-gate level Verilog netlist
library
Delay-minimized netlist from
Design Compiler

Phase I: Divide into alternate levels TCMS


of high (odd) and low (even) Vdd library
gates

Phase II: Linear programming


formulation

T≤Tmax no

yes
yes
P  
no
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Optimized netlist
Experimental Setup
• Switching activity at primary inputs set to 0.1
• Temperature: 75oC
• Technology node: 32nm
• Nominal-Vdd: (1.0V,0V), High-Vdd: (1.08V,-0.08V)
• Nominal-Vth: (0.29V,-0.25V),
High-Vth: (0.45V,-0.40V)
• Cell libraries characterized using HSPICE based
on PTM1 in Synopsys-compatible format
• Interconnect delay and load modeled
• 5 sizes for logic gates: X1, X2, X4, X8 and X16

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1http://www.eas.asu.edu/~ptm/
Applying Methodology to c17
e nor10011
e
b X2 X1 nor11011
b
X1 X1
inv101
d d
X8 X2
X2 X1

nor01100
X8 X2

inv101

nand01001
inv101
c b X2 c b X1
X16 X2
d inv101 d nor00111
X8 X4 nor10011 nand00110
X16 X8
X4 X4 X2 X1
inv101 nor01100
a a
X16 X8
X8 X2

X16 X8

Level: 1 2 3 4 inv101

Level : 1 2 3 4

Delay-minimized netlist Power-optimized netlist


Power : 283.6uW (leakage power: Power : 149.9uW (leakage power: 2.0uW,
10.3uW, dynamic power: 273.3uW) dynamic power: 147.9uW) 43
Area: 538 fins Area: 216 fins
Multi-Vdd Multi-Vth (1.3Tmin)

44
Multi-Vdd Single-Vth (1.3Tmin)

45
Fin-count Savings (1.3Tmin)

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Conclusions
• FinFETs are a necessary step in the evolution of
semiconductors because bulk CMOS has difficulties in
scaling beyond 32 nm
• Use of the back gate leads to very interesting design
opportunities
• Rich diversity of design styles, made possible by
independent control of FinFET gates, can be used
effectively to reduce total active power consumption
• IG/LP mode circuits provide an encouraging tradeoff
between power and area
• TCMS able to reduce both delay and subthreshold
leakage current in a logic circuit simultaneously

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