Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Design
Niraj K. Jha
Dept. of Electrical Engineering
Princeton University
3
Different Types of DG-FETs
Si Fin
5
FinFET 3-D Structure
7
FinFET Width Quantization
10
Low-power Design Techniques
• Standby mode
– Examples: Sleep transistor insertion, clock gating,
minimum leakage vector application
– Interfere with (disable/slow) circuit operation
– Do not address active mode leakage
• Active mode: Circuit optimization
– Examples: Gate sizing, Multiple Vdd/Vth
– Respect circuit operations and timing constraints
– Can be used to reduce active mode leakage
11
Talk Outline
• Background
• Motivation: Power Consumption
• FinFETs for Low Power Design
• Vth Control through Multiple Vdd’s
(TCMS)
• Extension of TCMS to Logic Circuits
• Conclusions
12
FinFETs for Low-power Design
• FinFET device characteristics can be
leveraged for low-power design
– Static threshold voltage control through back-
gate bias
– Area-efficient design through merging of
parallel transistors
• Independent control of FinFET gates also
provides novel circuit design opportunities
13
Logic Styles: NAND Gates
IG-mode
pull up
pull up bias
voltage
15
FinFET Characteristics
†B. Swahn and S. Hassoun, ``Gate sizing: FinFETs vs 32nm bulk MOSFETs,” in Proc. DAC, 2006
18
Our Approach
• Construct FinFET-based
32 nm PTM
32nm PTM Logic
Logicgate
gate Synopsys technology libraries
inFET models
FinFET
FinFETmodels
models designs
designs • Extend linear programming
based cell selection† for FinFETs
Delay/power • Use optimized netlists to
characterization in compare logic styles at a range
Benchmark
SPICE of delay constraints
Minimum-delay SG-mode
IG SG synthesis in netlist
Synopsys libraries Design Compiler
Power-optimized
IG/LP LP
mixed-mode netlists
Available modes
Available modes
22
Talk Outline
• Background
• Motivation: Power Consumption
• FinFETs for Low Power Design
• Vth Control through Multiple Vdd’s
(TCMS)
• Extension of TCMS to Logic Circuits
• Conclusions
23
Future of Interconnect Power
power principle:
1.08V 1V
– 1.0V Vdd for critical logic, Leakage
0.7V for off-critical paths current
Vin
• Our proposal:
overdriven gates
– Overdriven FinFET gates
leak a lot less! Overdriven
inverter
26
TCMS
• Using only two Vdd’s saves leakage only in
P-type FinFETs, but not in N-type FinFETs
• Solution
– Use a negative ground voltage (VHss) to
symmetrically save leakage in N-type FinFETs
– Vdd > Vdd
H L Vdd
H VddL
29
Link Design
• SPICE simulation to minimize power
consumption in TCMS link while remaining
within 1% of the delay of the single Vdd link
Single
Parameter TCMS Change
Vdd
0.199m
Link length(lopt) 0.199mm 0
m
Inverter widths
42, 84 30, 50 -36.5%
(s1, s2)
Delay (ps) 12.19 12.27 0.65%
Power (μW) 1080 647 -40% 30
Interconnect Synthesis
• Problem: Insert buffers on a given wiring
tree to meet a given delay bound while
minimizing total power consumption
• Two types of buffers considered
– TCMS buffers
– Dual-Vdd buffering scheme†
• A van Ginneken-style dynamic
programming buffer insertion algorithm
developed
†Y. Hu et al, Fast Dual-Vdd Buffering based on Interconnect Prediction 31
and Sampling, SLIP 2007
Power Savings
Power Savings
component
Dynamic -29.8%
power
Leakage 57.9%
power
Total power 50.4%
600000
Number of fins
500000
400000
100000
0
p1 r1 p2 r2 r3 r4 r5 Average
35
TCMS Extension
H
Vdd • VddH=1.08V
VLdd • VssH= -0.08V
V1
H
Vss V1' • VddL =1.0V
H
Vdd • VssL=Gnd
V2'
V2 L
Vss
H
Vss
• Overdriven gates are faster
I D (VGS Vt )
• Overdriven gates leak less I L exp(VGS Vt ) 36
Logic Library Design
L H
Vdd Vdd
a a
b b
L
Vss VHss
a a
b b
L
Vss VHss
a a
b b
L
Vss VHss
• Two-input NAND gate of a given size has five design variables:
– Supply voltage
– Gate input voltage for input-a
– Gate input voltage for input-b
– Vth for FinFETs connected to input-a
39
– Vth for FinFETs connected to input-b
Logic Library Design (Contd.)
L
Vdd
L
Vss
T≤Tmax no
yes
yes
P
no
41
Optimized netlist
Experimental Setup
• Switching activity at primary inputs set to 0.1
• Temperature: 75oC
• Technology node: 32nm
• Nominal-Vdd: (1.0V,0V), High-Vdd: (1.08V,-0.08V)
• Nominal-Vth: (0.29V,-0.25V),
High-Vth: (0.45V,-0.40V)
• Cell libraries characterized using HSPICE based
on PTM1 in Synopsys-compatible format
• Interconnect delay and load modeled
• 5 sizes for logic gates: X1, X2, X4, X8 and X16
42
1http://www.eas.asu.edu/~ptm/
Applying Methodology to c17
e nor10011
e
b X2 X1 nor11011
b
X1 X1
inv101
d d
X8 X2
X2 X1
nor01100
X8 X2
inv101
nand01001
inv101
c b X2 c b X1
X16 X2
d inv101 d nor00111
X8 X4 nor10011 nand00110
X16 X8
X4 X4 X2 X1
inv101 nor01100
a a
X16 X8
X8 X2
X16 X8
Level: 1 2 3 4 inv101
Level : 1 2 3 4
44
Multi-Vdd Single-Vth (1.3Tmin)
45
Fin-count Savings (1.3Tmin)
46
Conclusions
• FinFETs are a necessary step in the evolution of
semiconductors because bulk CMOS has difficulties in
scaling beyond 32 nm
• Use of the back gate leads to very interesting design
opportunities
• Rich diversity of design styles, made possible by
independent control of FinFET gates, can be used
effectively to reduce total active power consumption
• IG/LP mode circuits provide an encouraging tradeoff
between power and area
• TCMS able to reduce both delay and subthreshold
leakage current in a logic circuit simultaneously
47