Challenges of CMOS technology

Figure Main challenges for CMOS technology at the 21-nm technology node.
(YI SONG et al., 2011). Mobility Enhancement Technology for Scaling of CMOS
Devices: Overview and Status.
1. Carrier-Transport of CMOS using New Channel
Materials and Structures

 Carrier-transport-enhanced CMOS structures on the Si platform for

future high performance and low power LSIs

nMOSFET pMOSFET
Channel direction - <100> on (100) surface
<110> on (110) surface
Surface orientation (100) (110)
Strain in Si/Ge bi- or uni-axial tensile bi-axial tensile uni-axial
compressive
Materials III-V SiGe/Ge
Table ways to enhance carrier transport properties in MOS channels.
(Takagia et al., 2007). Carrier-Transport-Enhanced CMOS using New Channel
Materials and Structures.
A) Challenges for III-V CMOS

I. InGaAs Quantum Well Channel

II. InAlAs insulator (poor jox)
III. Non-self aligned contacts

Figure cross section of CMOS

(credit to www3.nd.edu)
B) Challenges for Ge channel materials

Advantages:
i. Best hole mobility (unlike III-V)
ii. Si(Ge) already used in logic technology
iii. Col-IV: Non-Polar

Challenges:
 Reference device is highly strained silicon

 Poor HiK interface:

• Need better understanding
• Buried strained QW Ge

 Higher dielectric constant

• Poorer SCE

 Worse parasitic resistance

• Worse dopant activation
 Figure schematic diagram of three types of device engineering
(Takagia et al., 2007). Carrier-Transport-Enhanced CMOS using New
Channel Materials and Structures.
 2. HYBRID-ORIENTATION CHANNEL
• Because of the low oxide-interface charge density and the highest electron mobility, a silicon
substrate oriented along the (100) crystalline plane is desirable for nMOS devices.

• To take full advantage of electron and hole mobility, nMOS devices should be fabricated on
Si(100) and pMOS devices on Si(110).

Hybrid- wafer bonding and

orientation selective silicon
Compatible with epitaxy are utilized
existing VLSI
technology to improve the
technology. (HOT) mobilities in nMOS
and pMOS devices.

Symmetrical compatible with

performance of dual stress liners,
nMOS and pMOS which further
devices is improve carrier
achieved. mobility by local
strain engineering.
 3. Design for manufacturing

Layout optimization becomes more and more

important for within chip variation reduction.

Litho OPC (optical proximity correction) has now been applied for several
node generations & design optimization of other process areas such as RIE,
RTA, CMP and epitaxial film growth are increasingly
used in recent generations.
 4. Multi‐Gate Fin Transistor
Multi-Gate Transistors have better SCE:
– Gates reduce spread of Vdrain Enables lower threshold voltage
– Enable lower channel doping ( ↑μ)

Multi-Gate Transistors have lower Eeef:

– Optimum gate work function is away from band-edge leading to
lower Eeff (↑μ)

Figure Multi‐Gate Transistor Architecture

(Credit to www3.nd.edu)
Multi-Gate Fin Transistor: Top Challenges for Multi‐Gate Fin Transistors:

 Self Aligned structure for Source / Implement High Strain in Fins

Drain  High Parasitics in Fin Transistors
 Non-Planar structure  Manufacturing worthy Patterning
 Design

Figure Multi-Gate Fin Transistor

(Credit to www3.nd.edu)
 5. Tunnel Transistors

Ultimate transistors may need tunnel injection at ultra-low Vcc. Would need new materials with
more efficient tunneling and atomic scale fabrication control

Band‐to‐Band Tunneling (BTBT) Transistor suffer from extremely poor drive current
 Need materials with more efficient tunneling

Figure Basic BTBT structure

(credit to www3.nd.edu)
Band bending allows tunneling at source channel interface
 Gate controlled band tunneling

Figure the structure and energy band diagram of

BTBT Transistor
(credit to www3.nd.edu)