Pentium™ Processor Fundamentals: PC Architecture For Technicians: Level-1

Chapter 10
Pentium™ Processor
Fundamentals
PC Architecture for
Technicians: Level-1
Systems Manufacturing Training
and Employee Development
Copyright © 1996 Intel Corp.
PC Architecture For Technicians Level-1

Rev. 1.0 Sys MFG T/ED 4/7/2019 Technical Excellence Development Series
Ch 10 - Page 1
Introduction
 The knowledge acquired here about the Pentium™
processor features, architecture, signals and key
bus cycles will serve a foundation for the boards
based on this processor.
 This overview will describe the features of the
Pentium as used in a typical Single Processor PC
system in Real Mode.
 Multiprocessor support signals and MESI protocol
signals are beyond the scope of this course.
 Protected Mode Registers and related features are
beyond the scope of this course.

Ch 10 - Page 2
OBJECTIVES: At the end of this section, the
student will be able to do the following:
 Describe the basic architecture of the Pentium
processor.
 Explain the use of the Pentium Registers.
 Describe the various Pentium buses.
 Explain the use of the Byte Enables .
 Discuss Pentium address generation.
 Discuss Pentium Bus Cycle Definitions.
 Describe Pentium Single & Burst cycles.
 Discuss Pentium Signal Descriptions.

Ch 10 - Page 3
Intel Family
Comparison
Ch 10 - Page 4
The Intel 86 Family of Processors
Internal External
Processors Year Architecture Bus Size Transistors Principle Features
86 1978 16 16 29K 16-bit architecture, basic
segment protection
88 1979 8 8 29K Same as 86, but with 8-bit
processor bus. (IBM PC)
286 1982 16 16 130K Expands segmentation
protection, adds single-
instruction task switching
(used in IBM PC/AT)
Intel 386TM 1985 32 32 375K Adds paging, 32-bit

extensions, on-chip address
translation, and greater
speed to 286 functions
Intel 386TM 1988 32 16 375K Same as Intel 386

SX processor, but with a 16-bit
data bus

Ch 10 - Page 5
The IntelTM 86 Family of Processors
Internal External
Processors Year Architecture Bus Size Transistors Principle Features
Intel 486TM 1989 32 32 1,200K Adds on-chip cache, floating-
DX point unit, and greater speed
to Intel386TM
Intel486TM 1991 32 32 No math, Lower cost

SX
Intel486TM 1992 32 32 1.2 Meg Double internal speed
DX-2
PentiumTM 1993 32 64 3.1 Meg Superscaler, Code & Data
P5 - 60,66 Cache, 64 bit data bus
PentiumTM 3.3v, Power Mgt,
P54C 1994 32 64 3.3 Meg Multiprocessor support
PentiumTM On Chip L1 & L2,

Pro 1995 32 64 CPU
5.5 Meg Dynamic Execution
GTL logic

Ch 10 - Page 6
Intel Family Comparison
Intel iCOMP Index

386 DX 25
486 SX25
DX2 66
DX4 100
Pentium 60
Pentium 66
Pentium 90
Pentium 100
0 200 400 600 800 1000

Ch 10 - Page 7
THE iCOMP(TM) INDEX
 iCOMP
 (Intel COmparative Microprocessor Performance).
 The iCOMP index is a simple numerical index of relative
performance for making straightforward comparisons of
Intel CPU power.
 The base processor for the iCOMP index is the 25-MHz
Intel486TM SX processor, which has been assigned a
value of 100.
 The size of the disparity between any two indices provides a
relative measure of how much more powerful one CPU is than
any other.
 It is an index that reflects the relative performance of one
Intel microprocessor to another, not system performance.
Ch 10 - Page 8
Pentium™
Processor
Architecture
Ch 10 - Page 9
Pentium™ Processor Architecture
Code Cache Branch
Prediction
32 bits
64 bits
256 bits
Prefetch
Buffers
Pipelined
U pipe V pipeline
Floating-Point
Unit
64 bit bus Integer Integer
Interface ALU ALU
Multiply
Register Set
Add
Divide
Data Cache

Ch 10 - Page 10
 The Pentium processors have a data bus of 64 bits.
 This is a 32 bit CPU due to having 32 bits registers.
 A standard Single Transfer Cycle can read or write up to
64 bits at a time (8 bytes)
 Burst read and burst write-back cycles are supported
by the Pentium processors.
 Burst Mode cycles are used for Cache operations and
transfer 32 bytes in 4 clocks (4 * 8 bytes = 4 * 64 bits).
 32 bytes is the size of the Pentium Cache line.
 For the Pentium, all cache operations are burst cycles.

Ch 10 - Page 11
Code Cache
Branch
Prediction
Separate Code and Data
caches
•On chip 8KB code and 8KB Prefetch
write back data cache.
•Two way set associative.
Buffers
•MESI Cache protocol U pipeline V pipeline Pipelined
Floating-Point
32 bits 64 bit bus Integer Integer
Interface Unit
64 bits ALU ALU
256 bits
Register Multiply
Set Add
Divide
Data Cache

Ch 10 - Page 12
 Pentium processors include separate Code and Data
Caches which can be enabled or disabled by software
or hardware.
 Each cache is 8-Kbytes in size, with a 32-byte line size
and is 2-way set associative (4K/way).
 The Data Cache is configurable to be write-back or
write-through on a line-by-line basis and follows MESI
protocol.
 The Instruction Cache is an inherently write-protected
cache (read-only)

Ch 10 - Page 13
Technical Innovations...
•Branch prediction:
Processor makes
predictions on next
Code Cache
instruction to be executed Branch
via the BTB. Prediction
32 bits
64 bits Prefetch
256 bits Buffers
•Superscalar Architecture U pipeline V pipeline
•more than one execution unit Pipelined
64 bit bus
Integer Integer Floating-Point
Interface
ALU ALU
Unit
NOTE: The Instruction Decode
Unit is in the Prefetch Buffers Multiply
Pipeline Hardwired
on this diagram. sequence Register Set
Prefetch
Add Instructions
Decode1 Divide
Decode2
Execute Data Cache
Write Back

Ch 10 - Page 14
 Instructions are Fetched from the code cache or
from the external bus.
 The decode unit Decodes the prefetched instructions
so the Pentium processor can execute the instruction.
 Branch prediction is implemented with 2 Prefetch
Buffers and a Branch Target Buffer so the needed
code is almost always prefetched before it is needed for
execution.
 Instructions are executed in 1 of 2 pipelines (“u” & “v”
pipes) which share access to a single set of registers.
 No additional instructions can begin execution until both
execution units complete their operations.

Ch 10 - Page 15
 Pentium processors have two instruction pipelines.
 The u-pipe can Execute all integer and floating point
instructions.
 The v-pipe can Execute simple integer instructions and
the FXCH floating-point instructions.
 Pairing instructions in these two pipes enables the
Pentium to operate on 2 instructions at the same time
(Superscaler execution).
 The Control ROM unit has direct control over both
pipelines.
 The Control ROM contains microcode which controls
the sequence of operations that must be performed.

Ch 10 - Page 16
Pentium™
Processor
Registers
Ch 10 - Page 17
Pentium Registers
General Registers
31 23 16 15 8 7 0 16-BIT 32-BIT
AH AL AX EAX NOTE: All registers in

DX EDX REAL MODE DEFAULT
DH DL
to 16 bits wide.
CH CL CX ECX
BH BL BX EBX
EBP
ESI
EDI
ESP
Segment Registers Status and Control
CS
31 0
SS
EFLAGS
DS EIP
ES
FS
GS

Ch 10 - Page 18
Segmented Addressing
Code
Segment
CS Stack
SS
DS Segment
ES
FS Data
GS
Segment
Data
Segment
Data
Segment
Data
Segment

Ch 10 - Page 19
Segmented Addressing
NOTE: We will assume,
unless otherwise
stated, that all examples
reflect real mode.
Operand
15 0
Segment Register e.g - CS
15 0
Offset within segment e.g - IP

Ch 10 - Page 20
Pentium Registers (EFlags)
 The EFlags register is not a normal register but a
collection of FLAG BITS which indicate the result of
previous operations or the current state of the CPU.
 A FLAG is just a flip-flop in the CPU that is SET (1) or
RESET (0) [cleared] depending on the condition
produced by an instruction .
 Some Flags indicate the condition produced by the
previous instruction.
 e.g - Zero Flag: ZF=1 (True) if the result of the last
arithmetic or logical operation was Zero.
 Some Flags are used to control certain operations.
 e.g. - IF (Interrupts Enabled); Trap Flag; Direction Flag.

Ch 10 - Page 21
Pentium Registers (EFlags)
FLAGS
23 15 7
I I
V V
I A V R N O O O D I T S Z A P C
0 0 0 0 0 0 0 0 0 0 I I 0 0 0 1
D C M F T P P F F F F F F F F F
31 P F 0
L L
ID X ID Flag (CPUID support) DF C Direction Flag

VIP X Virtual Interrupt Pending IF X Interrupt Enable Flag
VIF X Virtual Interrupt Flag TF X Trap Flag
AC X Alignment Check SF S Sign Flag
VM X Virtual 8086 Mode ZF S Zero Flag
RF X Resume Flag AF S Auxiliary Carry Flag
NT X Nested Task PF S Parity Flag
IOPL X I/O Privilege Level CF S Carry Flag
S = Status Flag
OF S Overflow Flag
C = Control Flag
X = System Flag
Bit Positions shown as “0” or “1” are
Intel reserved.

Ch 10 - Page 22
Pentium Registers (Debug)
LEN R/W
3 3
LEN
2
R/W
2
LEN
1
R/W
1
LEN
0
R/W
0 0 0 GD 0 0 1 GE L G L G L G L G L
E 3 3 2 2 1 1 0 0
B B B B B B
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BT S D 0 1 1 1 1 1 1 1 1 3 2 1 0
Reserved
Reserved
DR3 - Breakpoint 3 Linear Address

Ch 10 - Page 23
Pentium Registers (Debug)
 The Debug Registers provide hardware support for
setting breakpoints.
 You can define up to four breakpoints using Debug
Registers (DR0 - DR3).
 The Debug Registers store the Linear Address.
 The linear address is the address after the addition of the
Segment Base & the Offset (w/o Paging).
 This is the Physical Address in REAL MODE.
 When the Pentium address matches an address in
one of the Debug Registers, the Pentium issues a
Debug Exception (INT 1).
 This feature is used with the ITP Debug Tool.
Ch 10 - Page 24
Pentium™
Bus
Description
Ch 10 - Page 25
Bus Description
Pentium™ Processor with 64 Bit Wide Memory
D63:0
Pentium™ 64 bit
Processor A31:3, BE7#:0# Memory

Ch 10 - Page 26
Bus Description
7 0
Data Types Byte Byte

Address N
15 7 0
Each location in High Low
Word
memory is Byte wide Byte Byte
Address Address
N+1 N
31 15 0
High Word Low Word Doubleword
Address Address Address Address
N+3 N+2 N+1 N
63 47 31 15 0
Low Doubleword
Quadword
High Doubleword
“Chunk”
Address Address Address Address Address Address Address Address
N+7 N+6 N+5 N+4 N+3 N+2 N+1 N

Ch 10 - Page 27
Bus Description
FFFFFFFFH FFFFFFF8H
Physical Memory PHYSICAL

Space MEMORY
4GB
00000007H 00000000H
FFFFFFFFH FFFFFFF8H
00000007H 00000000H
BE7# BE6# BE5# BE4# BE3# BE2# BE1# BE0#
64-BIT Wide Memory

Organization
Ch 10 - Page 28
CPU Bus Description
 I/O Address Space is limited to 64 Kbytes (0000H-FFFFH).
 This limit is imposed by a 16 bit CPU Register.
 A 16 bit register can store up to FFFFH (1111 1111 1111 1111 y).
 Which CPU Register limits I/O space to 64K?
Not
Accessible
0000FFFFH 0000FFFCH
64 KByte
00000003H 00000000H
I/O Space
Ch 10 - Page 29
CPU Bus Description
 Address bus: The microprocessor provides an
address to the memory & I/O chips.
 The number of address lines determines the
amount of memory supported by the processor.
 A31:A3 Address bus lines (output except for
cache snooping) determines where in the 4GB
memory space or 64K I/O space the processor is
accessing.

Ch 10 - Page 30
CPU Bus Description
 The Pentium address consists of two sets of signals:
 Address Bus (A31:3)
 Byte Enables (BE7#:0#)
 Since address lines A2:0 do not exist on the Pentium, the
CPU uses A31:3 to identify a group of 8 locations known as
a Quadword (8 bytes -- also know as a “chunk”).
 Without A2:0, the CPU is only capable of outputting
every 8th address. (e.g. 00H, 08H, 10H, 18H, 20H, 28H, etc.)
 A2:0 could address from 000 to 111 in binary (0-7H)
3 = 011 7 = 111
2 = 010 6 = 110
1 = 001 5 = 101
0 = 000 4 = 100

Ch 10 - Page 31
Example Addresses Output by CPU
Output on CPU Address Lines for
addresses within a Quadword
Addresses 00000000 - 000000F
Addr to be Output Addr Placed on Addr to be Output Addr Placed on
(in Hex) CPU Addr Bus (in Hex) CPU Addr Bus
0000 0000 0000 0000 0000 0008 0000 0008
0000 0001 0000 0000 0000 0009 0000 0008
0000 0002 0000 0000 0000 000a 0000 0008
0000 0003 0000 0000 0000 000b 0000 0008
0000 0004 0000 0000 0000 000c 0000 0008
0000 0005 0000 0000 0000 000d 0000 0008
0000 0006 0000 0000 0000 000e 0000 0008
0000 0007 0000 0000 0000 000f 0000 0008

Ch 10 - Page 32
Example Addresses Output by CPU
Output on CPU Address Lines for
addresses within a Quadword
Addresses 00000010 - 000001F
Addr to be Output Addr Placed on Addr to be Output Addr Placed on
(in Hex) CPU Addr Bus (in Hex) CPU Addr Bus
0000 0010 0000 0010 0000 0018 0000 0018
0000 0011 0000 0010 0000 0019 0000 0018
0000 0012 0000 0010 0000 001a 0000 0018
0000 0013 0000 0010 0000 001b 0000 0018
0000 0014 0000 0010 0000 001c 0000 0018
0000 0015 0000 0010 0000 001d 0000 0018
0000 0016 0000 0010 0000 001e 0000 0018
0000 0017 0000 0010 0000 001f 0000 0018

Ch 10 - Page 33
CPU Bus Description
 The Pentium uses Byte Enables to address
locations within a QWORD.
 BE7#:BEO# (outputs): Byte enable lines - to enable
each of the 8 bytes in the 64-bit data path.
 In effect a decode of the address lines A2-A0 which the
Pentium does not generate.
 Which lines go active depends on the address, and
whether a byte, word, double word or quad word is
required.

Ch 10 - Page 34
Relationship of Byte Enables to
Locations Addressed within a QWORD
Byte Enable Data Path Used Location in Qword

BE0# D07:00 FIRST
BE1# D15:08 SECOND
BE2# D23:16 THIRD
BE3# D31:24 FOURTH
BE4# D39:32 FIFTH
BE5# D47:40 SIXTH
BE6# D55:48 SEVENTH
BE7# D63:56 EIGHT

Ch 10 - Page 35
Pentium Processor Addressing Examples
 Relationship of Addresses, Byte Enables, and
locations accessed.
 1 byte @ 12301000 (BE0#)
 1 word starting at FE025606 (BE7# & BE6#)
 8 bytes starting at 80000108 (BE7# through BE0#)
 1 word starting at 0A5D0F0D (BE6# & BE5#)
7 6 5 4 3 2 1 0
F E D C B A 9 8
Locations
Addr A31:3 BE7# BE6# BE5# BE4# BE3# BE2# BE1# BE0# Addressed
12301000 1 1 1 1 1 1 1 0 12301000
FE025600 0 0 1 1 1 1 1 1 FE025606, FE025607
80000108 0 0 0 0 0 0 0 0 80000108 - 8000010F
0A5D0F08 1 0 0 1 1 1 1 1 0A5D0F0D, 0A5D0F0E

Ch 10 - Page 36
Pentium Processor Addressing Examples
 Example Assembly Language Instructions and the
resultant Addresses & Byte Enables. (Assume DS=0)
 MOV AL, [0100] -1 byte @ 00000100 (BE0#)
 MOV BH, [0105] -1 byte @ 00000105 (BE5#)
 MOV AX, [0104] - 1 word starting at 00000104 (BE4# & BE5#)
 MOV EAX, [0100] -1 dword starting at 00000100 (BE0# through BE3#)
107 ------------------- 100

B B B B B B B B
E E E E E E E E
Addr on A31:3 Instruction 7 6 5 4 3 2 1 0 Locations Addressed
# # # # # # # #
00000100 MOV AL, [0100] 1 1 1 1 1 1 1 0 00000100 - 8 BIT

00000100 MOV BH, [0105] 1 1 0 1 1 1 1 1 00000105 - 8 BIT
00000100 MOV AX, [0104] 1 1 0 0 1 1 1 1 00000104, 00000105 - 16 BIT
00000100 MOV EAX, [0100] 1 1 1 1 0 0 0 0 00000100 TO 00000103 - 32 BITS

Ch 10 - Page 37
CPU Bus Description
Data bus: The data bus provides a path for data to flow.
 The data can flow to/from the microprocessor during a
memory or I/O operation.
 D63:DO (bi-directional): The 64-bit data path to or from
the processor. The signal W/R# distinguishes direction.
 Control bus: The control bus is used by the CPU to
tell the memory and I/O chips what the CPU is doing.
 Typical control bus signals are these:
 ADS# (output): Signals that the processor is beginning a
bus cycle:
 BRDY# (input): This signal ends the current bus cycle and
is used to extend bus cycles. (Ready Logic next page)

Ch 10 - Page 38
Ready Logic State Machine Example
BRDY#
Zero WS ADS#
IOCHRDY Cache Read

0=Add Wait
States for
ISA BUS TW TW
TW= Time Wait
DRAM-Read
TW TW
ISA Bus Read

Access /EPROMs
TW TW
TW TW
TW

Ch 10 - Page 39
CPU Bus Description
 Control bus:(Cont.)
 Typical control bus signals are these: (Cont.)
 M/IO# (output): Defines if the bus cycle is a Memory access
or an Input/Output Port access.
 D/C# (output): Defines if the bus cycles is Data or Code for
Memory access.
 W/R# (output): Indicates if bus cycle is a Write or a Read
operation.
 Cache#. (output): Processor indication of internal
cacheability. Cache# and Ken# are used together to
determine of a read will be turned into a linefill. (Burst
cycle).

Ch 10 - Page 40
Pentium™
Bus
Cycles
Ch 10 - Page 41
Bus Cycles Definition
M/IO# D/C# W/R# Cache# Ken# Cycle Description No. of Transfers
0 0 0 1 x Interrupt Acknowledge 1 transfer each cycle
(2 locked cycles)
0 0 1 1 x Special Cycle 1
0 1 0 1 x I/O Read , 32-bits or less 1
Non Cacheable
0 1 1 1 x I/O Write , 32-bits or less 1
Non Cacheable
1 0 0 1 x Code Read, 64-bits, 1
Non Cacheable
1 0 0 x 1 Code Read, 64-bits, 1
Non Cacheable
1 0 0 0 0 Code Read , 256-bit burst 4
Line Fill
1 0 1 x x Intel Reserved (will not be n/a
driven by the Pentium™
processor).
1 1 0 1 x Memory Read, 64 bit or less, 1
Non Cacheable
1 1 0 x 1 Memory Read, 64 bit or less, 1
Non Cacheable
1 1 0 0 0 Memory Read, 256 bit burst 4
Line Fill
1 1 1 1 x Memory Write, 64 bit or less 1
Non Cacheable
1 1 1 0 x 256 bit Burst Write back 4
*Cache# will not be asserted for any cycle in which M/IO# is driven low, or for any cycle in which PCD is
driven high.
Ch 10 - Page 42
GENERIC DECODE LOGIC
 The system board contain some logic to decode the
BUS CYCLE DEFINITIONS of the CPU.
 The BUS CYCLE DEFINITIONS from the CPU are
VALID when ADS# is asserted (Logic 0).
 The drawing shows an example of logic that could be
used to decode the BUS CYCLE DEFINITIONS.
 The signals generated by the GENERIC DECODE
LOGIC would be used by the System Board to
generate signals such as I/O chip selects and DRAM
& PROM output enables.

Ch 10 - Page 43
M/IO#
D Q
D/C# D Q INTA
D Q
W/R#
ADS# 486 / P5
SPECIAL
IOR
0
e.g. 1 IOW
1
I/O WR @ Addr 43H
43H = 0100 0011y FETCH
486 / P5
INVALID
MEMR
MEMW
Ch 10 - Page 44
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 00 0 1 0 0 0 0 11
e.g. (0 0 0) DMA #1
I/O WR @ Addr 43H
(0 0 1) PIC #1
43H = 0100 0011y
(0 1 0) PIT
(0 1 1) Digital I/O - Kbd
(1 0 0) DMA Page
(1 0 1) PIC #2
(1 1 0) DMA #2
(1 1 1) FPU
IOR
IOW
Ch 10 - Page 45
Special Cycles Definition
M/IO# = 0, D/C# = 0, W/R# = 1
BE7# BE6# BE5# BE4# BE3# BE2# BE1# BE0# Special Bus Cycle
1 1 1 1 1 1 1 0 Shutdown
1 1 1 1 1 1 0 1 Flush
(INVD, WINVD instr.)
1 1 1 1 1 0 1 1 Halt
1 1 1 1 0 1 1 1 Writeback
(WBINVD Instruction)
1 1 1 0 1 1 1 1 Flush Acknowledge
(FLUSH# assertion)
1 1 0 1 1 1 1 1 Brach Trace Message

Ch 10 - Page 46
Special Cycles Definition
 Halt Cycle: CPU waits for INTR, NMI, Reset, or INIT.
 Generated when Pentium executes a HLT instruction.
 If interrupts are enabled, an INTR (e.g Timer Tick) will
force the microprocessor out of a halt.
 Shutdown Cycle: CPU waits for NMI, Reset, or INIT.
 Generated by the Pentium:
 Triple Fault: The CPU detects a further exception (e.g.
General Protection Fault, Invalid Op Code, Stack Overflow)
while executing the Double Fault Exception handler.
 Internal Parity Error detected by the CPU.
 Shutdown is decoded by the system board and
generates a soft reset (INIT to Pentium) in a PC.

Ch 10 - Page 47
CPU Bus Cycles
 A BUS CYCLE begins with the Processor driving
an address and status (Control signals) and
asserting ADS#.
 A BUS CYCLE ends when the last BRDY# is
returned to the Processor.
 A BUS CYCLE may have 1 or 4 data transfers.

 A SINGLE Cycle transfer is 64 bits maximum [8 bytes].
 The shortest cycle is 2 clocks
 A BURST Cycle transfer is 256 bits (4*64) [32 bytes]

Ch 10 - Page 48
Microprocessor Single Bus Cycle
MEMORY WRITE & READ WITH WAIT STATES
T1 T2 T2 Ti T1 T2 T2 T2 Ti
CLK
ADS#
WAIT IDLE WAIT WAIT IDLE
STATE STATE STATE STATE STATE
A31-A3 ADDR ADDR
Byte Byte
BE7:0# Enables Enables
W/R# WRITE READ
CACHE#
BRDY#
D63-D0 DATA DATA

FROM CPU TO CPU

Ch 10 - Page 49
Basic Burst Read Cycle
CYCLE CYCLE CYCLE CYCLE
1 2 3 4
T1 T2 T2 T2 T2 Ti Ti Ti Ti
CLK
ADS#
IDLE IDLE IDLE
STATE STATE STATE
A31-A3
ADDR
BE7:0#
CACHE#
W/R# READ
KEN#
BRDY#
D63-D0 DATA DATA DATA DATA
TO TO TO TO
CPU CPU CPU CPU

Ch 10 - Page 50
Basic Burst Cycle
 Burst Cycles can transfer larger quantities of data in
fewer clocks than single transfer cycles.
 e.g. - Single Cycle: 8 bytes (64 bits) in 2 clocks.
 4 Singles cycles = 32 bytes in 8 clocks.
 e.g. - Burst Cycle: 32 bytes (4*64 bits) in 5 clocks.
 The Pentium uses burst mode for:
 Cacheable read cycles
 Write-back cycles when writing back a cache line.
 Burst cycles are limited to an address area that begins
at a 32-byte limit and the system board must calculate
the other 3 burst addresses.

Ch 10 - Page 51
Basic Burst Cycle
 The system board must generate the subsequent
addresses(2nd, 3rd, 4th) in the following sequence.
 Address Output by Pentium
1st 2nd 3rd 4th
00H 08H 10H 18H
08H 00H 18H 10H
10H 18H 00H 08H
18H 10H 08H 00H
 This is required in order to fill the Pentium 32t (20H)

byte cache on 32 byte boundaries.
 e.g. 32 bytes for addresses 100H - 11FH
 100H, 108H, 110H, 118H; or 110H, 118H, 100H, 108H, etc

Ch 10 - Page 52
Basic Burst Cycle
 These addresses can be generated as follows:
 A3 toggles for every address; A4 toggles every OTHER address
A7 6 5 4 3 2 1 A0 Address Output by Pentium
0 0 0 0 0 0 0 0 00H 08H 10H 18H
0 0 0 0 1 0 0 0
0 0 0 1 0 0 0 0
0 0 0 1 1 0 0 0
A7 6 5 4 3 2 1 A0 Address Output by Pentium

0 0 0 0 1 0 0 0 08H 00H 18H 10H
0 0 0 0 0 0 0 0
0 0 0 1 1 0 0 0
0 0 0 1 0 0 0 0

Ch 10 - Page 53
Pentium™
Signal
Description
Ch 10 - Page 54
Pentium™ Signal Description
 This overview will describe the signals of the
Pentium as used in a typical Single Processor PC
system.
 Multiprocessor support signals and MESI protocol
signals are beyond the scope of this course.

Ch 10 - Page 55
Signal Description
Clock Probe Mode
Initialization TAP Port
Address Bus SMM
Address Mask FP Error Reporting
Internal Parity Error Interrupts
Address Parity Pentium™ Bus Arbitration
Data Bus Cache Flush
Data Parity Cache Snooping

Bus Cycles Definition Cache Control
Bus Control
See the Pentium Data Book
Hardware Interface section
for a complete description
of all signals.
Ch 10 - Page 56
Signal Description
 CLOCK
 CLK - Clock (Input)
 Fundamental Timing for the Pentium
 The CPU uses this signal as the internal processor clock.
 BF - Bus Frequency (Input)
 Bus Frequency determines the bus-to-core frequency ratio
 When BF is strapped to Vcc, the processor will operate at a
2 to 3 bus to core frequency ratio.
 When BF is strapped to Vss, the processor will operate at a
1 to 2 bus to core frequency ratio.
 What symptoms might be exhibited if this signal is
incorrect?

Ch 10 - Page 57
Signal Description
 Initialization
 RESET - (Input)
 Forces the CPU to begin execution at a known state.
 INIT - Initialization (Input)
 The Pentium processor initialization input pin forces the
Pentium processor to begin execution in a known state.
 The processor state after INIT is the same as the state after
RESET except that the internal caches, write buffers, and
floating point registers retain the values they had prior to
INIT.

Ch 10 - Page 58
Signal Description
 Address Bus
 A31:A3 - ADDRESS bus lines
 Output except for cache snooping
 The number of address lines determines the amount of
memory supported by the processor.
 Determines where in the 4GB memory space or 64K IO
space the processor is accessing.
 These are input lines when AHOLD & EADS# are active
for Inquire Cycles (snooping)

Ch 10 - Page 59
Signal Description
 Address Bus
 BE7#:BEO#: Byte Enable lines (Outputs)
 Byte Enables to enable each of the 8 bytes in the 64-bit
data path.
 Helps define the physical area of memory or I/O accessed.
 The Pentium uses Byte Enables to address locations within
a QWORD.
 In effect a decode of the address lines A2-A0 which the
Pentium does not generate.
 Which lines go active depends on the address, and whether
a byte, word, double word or quad word is required.

Ch 10 - Page 60
Signal Description
 Address Mask
 A20M#: Address 20 Mask (Input)
 Emulates the address wraparound at 1 MByte which occurs
on the 8086.
 When A20M# is asserted, the Pentium processor masks
physical address bit 20 (A20) before performing a lookup to
the internal caches or driving a memory cycle on the bus.
 A20#M must be asserted only when the processor is in real
mode.
 Internal Parity
 IERR# - Internal Error (Output)
 Alerts System of Internal Parity Errors

Ch 10 - Page 61
Signal Description
 Address Parity
 AP Address Parity (I/O)
 Bi-directional address parity pin for the address lines.
 Address Parity is driven by the Pentium processor with even
parity information on all CPU generated cycles in the same
clock that the address is driven
 Even parity must be driven back to the CPU during inquire
cycles on this pin in the same clock as EADS#.
 Not supported on all systems
 APCHK#: Address Parity Check Signal (Output)
 The status of the address parity check is driven on the
APCHK# output.
 Even Parity Checking
Ch 10 - Page 62
Signal Description
 Data Bus.
 D63:DO - Data Lines (I/O).
 The bi-directional 64-bit data path to or from the CPU.
 The signal W/R# distinguishes direction.
 During reads, the CPU samples the data bus when BRDY#
is asserted.
 DP7: DP0 - Data Parity (I/O)
 Bi-directional data parity pins for the data bus.
 Even Parity Check. One for each byte of the data bus
 Output on writes, Input on reads.
 Not supported on all systems.

Ch 10 - Page 63
Signal Description
 Bus Control
 ADS# - Address Strobe (output)
 Indicates that a new valid bus cycle is currently being driven
by the Pentium processor.
 The following are some of the signals which are valid when
ADS#=0
» Addresses (A31:3)
» Byte Enables (BE7#:0#)
» Bus Cycle definition (M/IO#; D/C#; W/R#, CACHE#)
 From power-on the ADS# signal should be asserted
periodically when bus cycles are running.

Ch 10 - Page 64
Signal Description
 Bus Control (Cont.)
 BRDY# - Burst Ready (Input)
 Transfer complete indication.
 The burst ready input indicates that the external system has
presented data on the data pins in response to a read or
that the external system has accepted the Pentium
processor data in response to a write request.
 This signal ends the current bus cycle and is used to extend
bus cycles to allow slow devices extra time.
 If LOW (non-burst cycles), this signal ends the current bus
cycle and the next bus cycle can begin.
 If HIGH the Pentium is prevented from continuing
processing and wait states are added.

Ch 10 - Page 65
Signal Description
 Bus Cycle Definition
 M/IO# - Memory or Input/Output (output)
 M/IO# distinguishes between Memory and I/O cycles.
 The memory/input-output is one of the primary bus cycle
definition pins.
» 1 = Memory Cycle
» 0 = Input/Output Cycle
 It is driven valid in the same clock as the ADS# signal is
asserted.

Ch 10 - Page 66
Signal Description
 Bus Cycle Definition (Cont.)
 D/C# - Data or Code (output)
 D/C# distinguishes between data and code or special cycles
(control)
 The data/code output is one of the primary bus cycle
definition pins.
» 1 = Data
» 0 = Code / Control
»Control for Interrupt Acknowledge or Special Cycles
asserted.

Ch 10 - Page 67
Signal Description
 W/R# - Write or Read (output)
 W/R# distinguishes between Write and Read cycles.
 Write/read is one of the primary bus cycle definition pins.
 1 = Write
 0 = Read
asserted.

Ch 10 - Page 68
Signal Description
 Cache# - Cacheability (output)
 Processor indication of internal cacheability.
 The L1 cache must be enabled using the CD bit in CR0 for
Cache# to be asserted low.
 The Cache# signal could also be described as the BURST
instruction signal, because the Cache# signal (qualified with
KEN#) results in a burst mode transfer of 32 bytes of code
or data.
 Cache# and Ken# are used together to determine if a read
will be turned into a linefill. (Burst cycle).
 During write-back cycles, the CPU asserts the CACHE#
signal (KEN# does not have to be asserted)

Ch 10 - Page 69
Signal Description
 NA# - Next Address (Input)
 Indicates external memory is prepared for a pipeline cycle.
 An active next address input indicates that the external
memory system is ready to accept a new bus cycle
although all data transfers for the current cycle have not yet
completed.
 When NA# is asserted, the Pentium supplies the address
for the start of the next transfer early, so that the memory
system can latch the new address before the transfer is
ready to start.
 A detailed discussion of Address Pipelining is beyond the
scope of this course.

Ch 10 - Page 70
Signal Description
 Lock# - Bus Lock (Output)
 The bus lock pin indicates that the current bus cycle is
locked, typically for a read-modify-write operation.
 The CPU will not allow a bus hold when LOCK# is asserted.
 Locked cycles are generated when the programmer prefixes
certain instructions with the LOCK prefix.
» e.g. LOCK INC [EDI] ;Increment a memory location
 Locked cycles are generated automatically for certain bus
transfer operations.
» Interrupt Acknowledge cycles
» The XCHG instructions when 1 operand is memory-based.
» See Pentium manual for more details.

Ch 10 - Page 71
Signal Description
 Cache Control
 KEN# - Cache Enable (Input)
 Indicates to the Pentium whether or not the system can
support a cache line fill for the current cycle.
 Cache# and Ken# are used together to determine if a read
will be turned into a linefill. (Burst cycle).
 WB/WT# - Write-back/Write-through (Input)
 This pin allows a cache line to be defined as a a write back
or write-through on a line by line basis.
 This signal is necessary for the implementation of the MESI
protocol.
 Detailed discussion of the MESI protocol is beyond the
scope of this course.
Ch 10 - Page 72
Signal Description
 Cache Snooping
 AHOLD - Address Hold (Input)
 Floats the address bus so an inquire cycle can be driven to
the Pentium.
 AHOLD allows another bus master (e.g. DMA ctlr) to drive
the CPU address bus with the address for an inquire cycle.
» Effectively changes address lines to inputs.
 All other signals remain active so data for previously sent
bus cycles can still be transferred.
 EADS# - External Address Strobe (Input)
 Indicates that a valid external address has been driven onto
the CPU address pins for a snoop inquire cycle.
 Recognized while AHOLD is asserted.
Ch 10 - Page 73
Signal Description
 Cache Snooping (Cont.)
 HIT# - On Chip Cache hit (Output)
 Inquire Cycle Hit/Miss Indication
 Externally indicates whether an inquire cycle resulted in a
hit or miss.
 HITM# - On Chip Cache Hit Modified (Output)
 Hit/Miss to a modified line
 Externally indicates whether an inquire cycle hit a modified
line in the data cache.
 HITM# is never asserted without HIT# also being asserted

Ch 10 - Page 74
Signal Description
 Cache Flush
 Flush# - Cache Flush (Input)
 Writes all modified lines in the data cache back and flushes
the code and data caches.
 A Flush Acknowledge special cycle will be generated by the
Pentium™ indicating completion of the invalidation and
writeback.

Ch 10 - Page 75
Signal Description
 Bus Arbitration
 HOLD - Bus Hold (Input)
 Allows another bus master complete control of the CPU
bus.
 In response to the bus hold request, the Pentium processor
will float most of its output and input/output pins and assert
HLDA after completing all outstanding bus cycles.
 The Pentium processor will maintain its bus in this state
until HOLD is de-asserted.
 HLDA - Bus Hold Acknowledge (Output)
 External indication that the Pentium™ outputs are floated.

Ch 10 - Page 76
Signal Description
 Bus Arbitration (Cont.)
 BOFF# - Backoff (Input)
 Forces the Pentium to get off the bus in the next clock.
 After BOFF# is removed, the Pentium restarts the bus
cycle.
 BREQ - Bus Request (output)
 Indicates externally when a bus cycle is pending internally.
 Used to inform the arbitration logic that the Pentium need
control of the bus to perform a bus cycle.

Ch 10 - Page 77
Signal Description
 Interrupts
 INTR - Maskable Interrupt (Input)
 Indicates that an external interrupt has been generated.
 If the IF(Interrupt Enable Flag) bit in the EFLAGS register is
set, the Pentium processor will generate two locked
interrupt acknowledge bus cycles (to get type number) and
vectors to an interrupt handler after the current instruction
execution is completed.
 NMI - Non-Maskable Interrupt (Input)
 Indicates that an external non maskable interrupt has been
generated.
 The Pentium processor will vector to a Type 2 interrupt
handler after the current instruction execution is completed.

Ch 10 - Page 78
Signal Description
 Floating Point Error Reporting
 FERR# - Floating Point Error (Output)
 FERR# is included for compatibility with systems using
DOS-type floating point error reporting (IRQ13)
 Indicates that an unmasked error occurred
 FERR# is similar to the ERROR# pin on the Intel387TM math
coprocessor.
 IGNNE# - Ignore Numeric Exception (Input)
 Indicates ignore numeric exception.
 Valid only when CR0 NE bit is reset.
 Permits processor to continue execution before the floating
point interrupt service routine has cleared the error.

Ch 10 - Page 79
Signal Description
 System Management Mode
 SMI# - System Management Mode Interrupt (Input)
 Latches a System Management Interrupt Request
 When the latched SMI# is recognized on an instruction
boundary, the processor enters System Management
Mode
 SMIACT# - Sys Mgt Interrupt Active (Output)
 Indicates that the processor is operating in SMM.

Ch 10 - Page 80
Signal Description
 Test Access Port (TAP)
 Signals for Hardware Debug Support (ITP) & Boundary
Scan Testing.
 TCK - Testability Clock Input (Input)
 The testability clock input provides the clocking function for
the Pentium processor boundary scan in accordance with
the IEEE Boundary Scan interface.
 TMS - Test Mode Select (Input)
 The value of the test mode select input signal sampled at
the rising edge of TCK controls the sequence of TAP
controller state changes.

Ch 10 - Page 81
Signal Description
 Test Access Port (TAP) (Cont.)
 TDI - Test Data Input (Input)
 The test data input is a serial input for the test logic.
 TAP instructions and data are shifted into the Pentium
processor on the TDI pin on the rising edge of TCK when
the TAP controller is in an appropriate state.
 TDO - Test Data Output (Output)
 The test data output is a serial output of the test logic.
 TAP instructions and data are shifted out of the Pentium
processor on the TDO pin on TCK’s falling edge when the
TAP controller is in the appropriate state.

Ch 10 - Page 82
Signal Description
 Test Access Port (TAP) (Cont.)
 TRST# - Test Reset (Input)
 When asserted, the test reset input allows the TAP
controller to be asynchronously initialized
 Probe Mode
 R/S# - Resume/Stop [Run/Scan] (Input)
 The run/stop input is an asynchronous, edge-sensitive
interrupt used to stop the normal execution of the processor
and place it into an idle state.
 PRDY - Probe Ready (Output)
 The probe ready output pin indicates that the processor has
stopped normal execution in response to the R/S# pin going
active. The CPU enters Probe Mode.
Ch 10 - Page 83
Pentium™
Address/Data
Bus Exercise
Ch 10 - Page 84
Pentium Address/Data Bus Exercise
Assume you used an ITP debug tool to write the
following into memory.
 Write 55H to 8 bytes @ 0:0 (0H-7H Physical)
 Write AAH to 8 bytes @ 0:8 (8H-0FH Physical)
 NOTE: Or vice versa (Address not significant)
Result after reading the memory written to above!
0x000000000000P 55 55 55 55 55 5d 55 55 'UUUUU]UU'
0x000000000008P aa aa aa aa aa ba aa aa '........'
 Using your knowledge of Pentium address & byte enable
generation, determine what Data Bus problem could cause the
bad data?
Hint: D63 .....................................D0
55 55 5d 55 55 55 55 55
Ch 10 - Page 85
Where to get more information
 Pentium™ Processor User’s Manual
 Order Number 241428
 Pentium™ Architecture & Programming Manual
 Order Number 241430
 Pentium™ Processor System Architecture
 Mindshare (ISBN 1-881609-07-3)
 The Indispensable Pentium™ Book
 Addison-Wesley (ISBN 0-201-87727-9)

Ch 10 - Page 86
SUMMARY
WE HAVE DISCUSSED THE FOLLOWING:
 The basic architecture of the Pentium processor.
 The use of the Pentium Registers.
 The various Pentium buses.
 The use of the Byte Enables .
 Pentium address generation.
 Pentium Bus Cycle Definitions.
 Pentium Single & Burst cycles.
 Pentium Signal Descriptions.

Ch 10 - Page 87

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Chapter 10

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

Intel 386TM 1985 32 32 375K Adds paging, 32-bit

Intel 386TM 1988 32 16 375K Same as Intel 386

PC Architecture For Technicians Level-1

Intel486TM 1991 32 32 No math, Lower cost

PentiumTM On Chip L1 & L2,

PC Architecture For Technicians Level-1

Intel iCOMP Index

0 200 400 600 800 1000

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

AH AL AX EAX NOTE: All registers in

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

ID X ID Flag (CPUID support) DF C Direction Flag

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

Data Types Byte Byte

PC Architecture For Technicians Level-1

Physical Memory PHYSICAL

64-BIT Wide Memory

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

Byte Enable Data Path Used Location in Qword

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

107 ------------------- 100

00000100 MOV AL, [0100] 1 1 1 1 1 1 1 0 00000100 - 8 BIT

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

IOCHRDY Cache Read

ISA Bus Read

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

(0 1 1) Digital I/O - Kbd

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

 A BUS CYCLE may have 1 or 4 data transfers.

PC Architecture For Technicians Level-1

W/R# WRITE READ

D63-D0 DATA DATA

PC Architecture For Technicians Level-1

D63-D0 DATA DATA DATA DATA

PC Architecture For Technicians Level-1

PC Architecture For Technicians Level-1

 This is required in order to fill the Pentium 32t (20H)

PC Architecture For Technicians Level-1