Contents

 Introduction.
 Uses and Needs.
 Types of HDL
Verilog HDL
VHDL
 Advantages of HDL.
 Disadvantages of HDL.
 Introduction
Hardware Description Language(HDL) :

 Hardware Description Language is a specialized

computer language used to program electronic and
digital logic circuits.
The structure ,operation and design of the circuits are
programmable using HDL.
A Hardware description language is similar to software
programming languages used for modelling the logical
function of digital circuits and systems.
 The principal feature of a hardware description
language is that it contains the capability to describe
the function of a piece of hardware independently of
the implementation.
 In electronics a HDL is a language from a class
of computer language for formal description of
electronic circuit.
 It can describe circuit operation, its design and tests
to It can describe circuit operation, its design and
tests to verify its operation at any level.
Software programming
language
 Language which can be
translated into machine
instructions and then
executed on a computer.
 Assembly language is the
lowest level language that a
CPU can actually understand
as each assembly instruction
translates to a single machine
code instruction.
 Written with the pure logical
or arithmetic thinking.
Hardware description
language
 Language with syntactic and
semantic support for modelling
the temporal behaviour and
spatial structure of hardware.
 HDL is a way of describing large
electronic schematic that is a
chip .
 Needs thorough working
knowledge of hardware circuits ,
we should able to predict how a
given code will be implemented
in hardware
NEED OF HDL
 Initially , in the late 70’s the circuit designers worked
on the printed circuit boards or on breadboards.
 The testing of large circuits was not possible because
the large circuits contain lots of gates and the response
of every gate could not be checked.
 Easy to design circuit through computer and then
implement on hardware

 It resembles a programming language, but is

specifically oriented to describing hardware
structures and behaviour.
 HDL can be used represent logic diagrams Boolean
expressions, and other more complex digital circuits.
 As documentation language ,HDL is used to
represent and document digital systems in a
form that can be read by both humans and
computers and is suitable as an exchange
language between designers.

 The language content can be stored and

retrieved easily and processed by computer
software in an efficient manner.

 There are two applications of HDL processing

: SIMULATION and SYNTHESIS.
 Types of HDL
 There are two standard HDL’s that are supported by
IEEE.
 VHDL(Very-High-Speed Integrated Circuits HDL)-
Sometimes referred to as VHSIC HDL , this was
developed from an initiative by US .of Defence .
 Verilog HDL-developed by Cadence Data Systems
and later transferred to a consortium called Open
Verilog International(OVI).
 Verilog
 The Verilog Hardware Description Language, usually just
called Verilog , was designed and first implemented by
Phil Moor by at Gateway Design Automation in 1984 and
1985.
 Verilog simulators are available for most computers at a
variety of prices, and which have a variety of performance
characteristics and features.
 Verilog is more heavily used than ever, and it is growing
faster than any other hardware description language.
 It has truly become the standard hardware description
language.
 VERILOG
 VERILOG HDL has a syntax that describes
precisely the legal constructs that can be used in
the language.
 It uses about 100 keywords pre-defined , lowercase
, identifiers that define the language constructs.
 Example of keywords : module , endmodule
,input, output wire , and ,or ,not ,etc .,
 Any text between two slashes(//)and the end line o
line is interpreted as a comment.
 Blank spaces are ignored and names are case
sensitive.
 Verilog- Module
 A module is the building block in Verilog.
 It is declared by the keyword module and is
always terminated by the keyword end
module.
 Each statement is terminated with a semi-
colon ,but there is no semi-colon after
endmodule.
 module half _adder(a, b, sum, carry);
 Input a , b;
 output sum;
 output carry;
 xor (sum , A, B);
 and(carry , A , B);

 endmodule
 VHDL
VHDL was developed by the VHSIC(very High Speed
integrated circuit) Program in the late 1970s and 1980s
• The VHSIC program was funded by the U.S Department of
Defence
• Existing tools were inadequate for complex Hardware
Designs
The evolution of VHDL has included the following mile
stones:
 In 1981, VHDL was first proposed as HDL
 In 1986, VHDL was proposed as an IEEE standard
 In 1987,the first VHDL standard was adopted
 In 1993, a revised VHDL standard was adopted
 VHDL TERMS
SYNTHESIS
Converting code to circuit.
SIMULATION
Giving Input and verifying the functionality of
circuit.
 VHDL is commonly used to write text models that
describe a logic circuit.
 VHDL
The fundamental unit of VHDL is called a signal . let’s
assume that signal can be either a 0 or 1
Some Basic VHDL Logic:
signal and_ gate : std_ logic ;
and_ gate <= input_1 and input_2;
The first line of code defines a signal of type std_ logic and it
is called and_ gate.
Std_ logic is the type that is most commonly used to define
signals
This code will generate an AND gate with a single output
(and_ gate) and 2 inputs (input_1 and input_2).
The keyword “and” is reserved in VHDL.
The <= operator is known as the assignment operator.
 VHDL
 Inputs and outputs to a file are defined in an entity. An
entity contains a port that defines all inputs and outputs to
a file.
entity example_ and is
port(
input_ 1 : in std_ logic;
input_ 2 :in std_ logic;
and_ result : out std_ logic
);
end example_ and;
 It is an basic entity , defines an entity called example_ and
and 3 signals,2 inputs and 1 output all of which are of std_
logic
 verilog VHDL

 Design is composed of  Design is composed of

entities each of which can modules which have just one
have multiple architectures. implementation

 Harder to learn and use.  Easy to learn and use.

 Verilog is based on C  VHDL is based on Pascal.

 ADVANTAGES OF HDL:

 Allow designers to talk about what the hardware

should do without actually designing the hardware
itself, or in other words HDLs allow designers to
seperate behaviour from implementation at various
levels of abstraction
 Designers can make decisions about cost ,
performance, power and area earlier in the design
process.
 Designer can create tools which automatically
manipulate the design for verification , synthesis ,
optimization
ADVANTAGES OF HDL :

 Increase flexibility to design changes.

 Better and easier design auditing and verification.

 DISADVANTAGES OF HDL :

 It can be time consuming

 Need to be familiar with algorithm and how to write it